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21. 发明授权

US06916721B2 Method for fabricating a trench capacitor with an insulation collar 失效
标题翻译：用于制造具有绝缘套圈的沟槽电容器的方法
公开(公告)号：US06916721B2
公开(公告)日：2005-07-12
申请号：US10722360
申请日：2003-11-26
申请人： Lars Heineck , Stephan Kudelka , Jörn Lützen , Hans-Peter Moll , Martin Popp , Till Schlösser , Johann Steinmetz
发明人： Lars Heineck , Stephan Kudelka , Jörn Lützen , Hans-Peter Moll , Martin Popp , Till Schlösser , Johann Steinmetz
IPC分类号： H01L21/20 , H01L21/334 , H01L21/425 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10867 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.
摘要翻译：一种在衬底中制造具有绝缘套环的沟槽电容器的方法，其使用具有相应掩模开口的硬掩模经由掩埋触点将其一侧的衬底电连接。

22. 发明授权

US06566193B2 Method for producing a cell of a semiconductor memory 有权
公开(公告)号：US06566193B2
公开(公告)日：2003-05-20
申请号：US10096473
申请日：2002-03-12
申请人： Franz Hofmann , Till Schlösser
发明人： Franz Hofmann , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10876
摘要： The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.

23. 发明授权

US06534820B2 Integrated dynamic memory cell having a small area of extent, and a method for its production 失效
标题翻译：具有小范围的集成动态存储单元及其制造方法
公开(公告)号：US06534820B2
公开(公告)日：2003-03-18
申请号：US09745565
申请日：2000-12-21
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser
IPC分类号： H01L29788
CPC分类号： H01L27/10844 , H01L27/108 , H01L27/10876
摘要： An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.
摘要翻译：描述在半导体衬底上具有小面积范围的集成动态存储单元。存储单元具有选择MOSFET，其具有连接到字线的栅极连接区域，连接到位线的源极连接掺杂区域和漏极连接掺杂区域。存储器MOSFET具有通过薄介电层连接到将存储器MOSFET的源极连接掺杂区域连接到选择MOSFET的漏极连接掺杂区域的连接掺杂区域的栅极连接区域。存储器MOSFET还具有连接到电源电压的漏极连接掺杂区域。选择和存储器MOSFET被布置在沟槽的相对的侧壁上，沟槽被蚀刻在衬底中，并且连接掺杂区域形成沟槽的底部。

24. 发明授权

US06274453B1 Memory cell configuration and production process therefor 有权
标题翻译：内存单元配置及其生产过程
公开(公告)号：US06274453B1
公开(公告)日：2001-08-14
申请号：US09405916
申请日：1999-09-24
申请人： Till Schlösser , Franz Hofmann , Wolfgang Krautschneider
发明人： Till Schlösser , Franz Hofmann , Wolfgang Krautschneider
IPC分类号： H01L2120
CPC分类号： H01L27/10876 , H01L27/10805 , H01L27/10808
摘要： A memory cell configuration with many ferroelectric or dynamic memory cells provided in a semiconductor substrate. Alternating trenches and lands extend parallel in a longitudinal direction of a main face of the semiconductor substrate. A channel stop layer is buried in the lands and divides the semiconductor substrate into a lower region that includes the trench bottoms and an upper region that includes the land ridges. First planar selection transistors with intervening trench channel stop regions are disposed along the trench bottoms. Second planar selection transistors with intervening land channel stop regions are disposed along the land ridges. The first and second selection transistors have respective source, gate, channel and drain regions, which are offset longitudinally from one another such that source and drain regions of the first and second selection transistors alternate in the transverse direction in the main face of the semiconductor substrate. Isolated word lines are provided which extend in the transverse direction along the main face for triggering the first and second selection transistors in the respective gate regions. Isolated bit lines are provided which extend in an oblique direction along the main face for connecting the first and second selection transistors in the respective source regions. And preferably ferroelectric capacitors are each connected to the drain regions of applicable selection transistors via capacitor contacts.
摘要翻译：具有设置在半导体衬底中的许多铁电或动态存储单元的存储单元配置。交替沟槽和焊盘在半导体衬底的主面的纵向方向上平行延伸。沟道阻挡层埋在焊盘中，并将半导体衬底分成包括沟槽底部的下部区域和包括焊盘脊的上部区域。具有中间沟槽沟道阻挡区域的第一平面选择晶体管沿沟槽底部设置。具有中间的槽脊通道停止区域的第二平面选择晶体管沿着脊脊布置。第一和第二选择晶体管具有各自的源极，栅极，沟道和漏极区域，它们彼此纵向偏移，使得第一和第二选择晶体管的源极和漏极区域在半导体衬底的主面中在横向方向上交替。提供隔离的字线，其沿着主面沿横向方向延伸，用于触发各个栅极区域中的第一和第二选择晶体管。提供了沿着主面沿倾斜方向延伸的隔离位线，用于连接各个源极区域中的第一和第二选择晶体管。并且优选地，铁电电容器通过电容器触点连接到适用的选择晶体管的漏极区域。

25. 发明授权

US06258658B1 Memory cell configuration and corresponding fabrication method 有权
标题翻译：存储单元配置及相应的制造方法
公开(公告)号：US06258658B1
公开(公告)日：2001-07-10
申请号：US09250362
申请日：1999-02-12
申请人： Thomas Böhm , Volker Weinrich , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Till Schlösser
发明人： Thomas Böhm , Volker Weinrich , Manfred Hain , Armin Kohlhase , Yoichi Otani , Andreas Rusch , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10823 , H01L27/10808
摘要： The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches. Insulation trenches for insulating the source/drain regions in the longitudinal direction of neighboring memory cells run in the transverse direction in the main surface of the semiconductor substrate. A respective, preferably ferroelectric, capacitor is connected to the source/drain region of the respective memory cell and is arranged above the word lines.
摘要翻译：存储单元配置在半导体衬底中具有多个优选铁电存储单元。相互并行的位线沟槽在半导体衬底的主表面中沿纵向延伸。位线设置在沟槽的底部。源极/漏极区域形成在沟槽的冠部中。通道区域设置在沟槽的壁中。在每种情况下，壁上的沟道区域被构造成使得相关存储单元的可驱动选择晶体管形成在其中，而另一壁上的沟道区域被配置为使得位于那里的晶体管闭合。用于驱动选择晶体管的绝缘字线通过位线沟槽沿着半导体衬底的主表面在横向方向上延伸。用于绝缘沟槽，用于使相邻存储单元的纵向上的源极/漏极区域绝缘，在半导体衬底的主表面中沿横向延伸。相应的优选铁电电容器连接到相应存储单元的源极/漏极区域并且被布置在字线之上。

26. 发明授权

US07045855B2 Semiconductor device and corresponding fabrication method 失效
标题翻译：半导体器件及相应的制造方法
公开(公告)号：US07045855B2
公开(公告)日：2006-05-16
申请号：US10777207
申请日：2004-02-13
申请人： Björn Fischer , Matthias Goldbach , Stefan Jakschik , Till Schlösser
发明人： Björn Fischer , Matthias Goldbach , Stefan Jakschik , Till Schlösser
IPC分类号： H01L29/792
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31612 , H01L21/31616 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10838 , H01L27/1087 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L28/56 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/66181 , H01L29/785
摘要： A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.
摘要翻译：具有栅极结构的半导体器件，所述栅极结构具有由第一材料制成的第一栅极电介质，所述第一材料具有位于所述沟道区域正上方的第一厚度和第一介电常数，以及由第二栅极电介质构成的覆盖的第二栅极电介质材料具有明显大于第一介电常数的第二厚度和第二介电常数; 并且第一栅极电介质的第一厚度和第二栅极电介质的第二厚度被选择为使得具有第一栅极电介质的栅极结构的相应厚度以获得相同的阈值电压至少与厚度等于第一厚度和第二厚度之和的厚度。本发明还涉及相应的制造方法。

27. 发明授权

US06873000B2 Storage cell field and method of producing the same 失效
标题翻译：储存池场及其生产方法
公开(公告)号：US06873000B2
公开(公告)日：2005-03-29
申请号：US10266188
申请日：2002-10-07
申请人： Matthias Goldbach , Till Schlösser
发明人： Matthias Goldbach , Till Schlösser
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/0218 , H01L27/10861 , H01L27/10867
摘要： A storage cell field has a plurality of storage cells formed in a substrate of a first doping type, said storage cells comprising a trench capacitor arranged in said substrate and a selection transistor associated with said trench capacitor and provided with a transistor body which is arranged in said substrate. An implantation having an increased dopant concentration of the first doping type is provided in said substrate. This implantation prevents space-charge zones, which are located at the trench capacitors and which are caused in predetermined storage states of said trench capacitors, from constricting a substrate region, which is available for applying a predetermined potential to the transistor bodies, in such a way that said predetermined potential cannot be applied.
摘要翻译：存储单元场具有形成在第一掺杂类型的衬底中的多个存储单元，所述存储单元包括布置在所述衬底中的沟槽电容器和与所述沟槽电容器相关联的选择晶体管，所述晶体管本体被布置在所述基板。在所述衬底中提供具有增加的第一掺杂类型的掺杂剂浓度的注入。这种注入防止位于沟槽电容器处并且在所述沟槽电容器的预定存储状态下引起的空间电荷区域将这种可用于向晶体管体施加预定电位的衬底区域收缩不能应用所述预定电位的方式。

28. 发明授权

US06861688B2 Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with a line configuration and method for fabricating a line configuration 有权
标题翻译：用于连接至少一个存储单元的位线的线路配置，具有线路配置的半导体部件和用于制造线路配置的方法
公开(公告)号：US06861688B2
公开(公告)日：2005-03-01
申请号：US10288387
申请日：2002-11-05
申请人： Dirk Manger , Till Schlösser
发明人： Dirk Manger , Till Schlösser
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10888 , H01L27/10885
摘要： A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory cell. A first bit line in a first bit line level is disposed below a second bit line in a second bit line level and the second bit line penetrates through the first bit line at at least one location of the first bit line for the purpose of producing a contact with the at least one memory cell at penetration locations. It is thus possible to provide space-saving structures, in particular sub-8F2 structures.
摘要翻译：用于接触连接至少一个存储器单元，特别是DRAM存储单元的位线配置具有位于存储单元的平面之上的位线。第一位线电平中的第一位线设置在第二位线电平中的第二位线下方，并且第二位线在第一位线的至少一个位置处穿过第一位线，以产生第在穿透位置处与至少一个存储单元接触。因此，可以提供节省空间的结构，特别是8F 2结构。

29. 发明授权

US06798000B2 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US06798000B2
公开(公告)日：2004-09-28
申请号：US10275337
申请日：2002-12-18
申请人： Richard Johannes Luyken , Till Schlösser , Thomas Peter Haneder , Wolfgang Hönlein , Franz Kreupl
发明人： Richard Johannes Luyken , Till Schlösser , Thomas Peter Haneder , Wolfgang Hönlein , Franz Kreupl
IPC分类号： H01L2976
CPC分类号： H01L51/0595 , B82Y10/00 , G11C2213/17 , H01L51/0048 , H01L51/0508 , Y10S977/938
摘要： A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.
摘要翻译：具有纳米线的场效应晶体管，其形成场效应晶体管的源极区，沟道区和漏极区，纳米线是半导体和/或金属导电的纳米线。场效应晶体管还具有形成场效应晶体管的栅极区域的至少一个纳米管，纳米管是半导体和/或金属导电的纳米管。纳米线和纳米管彼此间隔一定距离或以这样的方式设置，使得在纳米线和纳米管之间基本上不可能存在隧穿电流，并且纳米线的沟道区的导电性可以通过施加到纳米管的电压的结果通过场效应来控制。

30. 发明授权

US06737689B1 FEMFET device and method for producing same 失效
标题翻译： FEMFET器件及其制造方法
公开(公告)号：US06737689B1
公开(公告)日：2004-05-18
申请号：US09857262
申请日：2001-07-16
申请人： Till Schlösser , Thomas Haneder
发明人： Till Schlösser , Thomas Haneder
IPC分类号： H01L2976
CPC分类号： H01L21/28291 , H01L28/56 , H01L29/516
摘要： The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.
摘要翻译：本发明涉及具有半导体衬底和设置在半导体衬底中的至少一个场效应晶体管的FEMFET器件。场效应晶体管具有源极区域，漏极区域，沟道区域和栅极堆叠。栅极堆叠具有至少一个铁电层，并且至少一个薄扩散阻挡层被布置在最低铁电层和半导体衬底之间，并且被配置为使得铁电层的组分向半导体内扩散基本上被防止。

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