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21. 发明授权

US07867883B2 Methods of fabricating non-volatile memory devices 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07867883B2
公开(公告)日：2011-01-11
申请号：US12146653
申请日：2008-06-26
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Jin-Taek Park , Byeong-In Choe
IPC分类号： H01L21/425 , H01L29/06
CPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11551 , H01L27/11578 , H01L29/42352 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
摘要翻译：一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极在栅极结构的相对侧的有源区中的区域。源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。还讨论了相关设备。

22. 发明授权

US08675409B2 Non-volatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US08675409B2
公开(公告)日：2014-03-18
申请号：US13463060
申请日：2012-05-03
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，与有源区交叉的接地选择线，以及与有源区交叉并与地选线相隔的串选择线。多个存储单元字线可以与地线选择线和弦选择线之间的有源区域相交，并且与多个字线中的相邻字线之间以及多个存储单元字线中的最后一个之间提供大致相同的第一间隔和字符串选择行。可以在接地选择线和多个存储单元字线中的第一个之间提供第二间隔。

23. 发明申请

US20110031559A1 SEMICONDUCTOR DEVICES IN WHICH A CELL GATE PATTERN AND A RESISTOR PATTERN ARE FORMED OF A SAME MATERIAL AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：细胞栅格图案和电阻图案的半导体器件形成相同的材料及其形成方法
公开(公告)号：US20110031559A1
公开(公告)日：2011-02-10
申请号：US12905517
申请日：2010-10-15
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L28/20
摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, farming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.
摘要翻译：通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上耕作导电层，并且使导电层以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。

24. 发明授权

US07816245B2 Method of forming semiconductor devices in which a cell gate pattern and a resistor pattern are formed of a same material 有权
标题翻译：形成其中单元栅极图案和电阻器图案由相同材料形成的半导体器件的方法
公开(公告)号：US07816245B2
公开(公告)日：2010-10-19
申请号：US11648992
申请日：2007-01-03
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/3205
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L28/20
摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, forming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.
摘要翻译：通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上形成导电层，并且使导电层以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。

25. 发明授权

US07645644B2 Data line layout in semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件中的数据线布局及其形成方法
公开(公告)号：US07645644B2
公开(公告)日：2010-01-12
申请号：US12113994
申请日：2008-05-02
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052
摘要： In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n
摘要翻译：在一个方面，提供了一种半导体器件，其包括数据块，该数据块包括M个并行且顺序排列的数字线，编号为{0,1,2。。。 n，n + 1，。。。，m-1，m}，其中M，n和m是正整数，并且其中n

26. 发明授权

US08217467B2 Semiconductor memory devices 有权
标题翻译：半导体存储器件
公开(公告)号：US08217467B2
公开(公告)日：2012-07-10
申请号：US12984860
申请日：2011-01-05
申请人： Jong-Sun Sel , Jung-Dal Choi , Choong-Ho Lee , Ju-Hyuck Chung , Hee-Soo Kang , Dong-uk Choi
发明人： Jong-Sun Sel , Jung-Dal Choi , Choong-Ho Lee , Ju-Hyuck Chung , Hee-Soo Kang , Dong-uk Choi
IPC分类号： H01L21/70
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/76816 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.
摘要翻译：在一些实施例中，半导体存储器件包括包括单元阵列区域和外围电路区域的衬底。半导体存储器件还包括在衬底上的器件隔离图案。器件隔离图案限定了单元阵列区域内的第一有源区和第二有源区以及外围电路区中的第三有源区。半导体存储器件还包括第一有源区中的第一公共源极区，多个第一源极/漏极区和第一漏极区。半导体存储器件还包括第二公共源极区域，多个第二源极/漏极区域和第二有源区域中的第二漏极区域。半导体存储器件还包括第三有源区中的第三源/漏区。半导体存储器件还包括与第一和第二公共源极区域接触的公共源极线。

27. 发明申请

US20110318902A1 METHODS OF FABRICATING FLASH MEMORY DEVICES HAVING SHARED SUB ACTIVE REGIONS 有权
标题翻译：制造具有共享子活动区域的闪存存储器件的方法
公开(公告)号：US20110318902A1
公开(公告)日：2011-12-29
申请号：US13230978
申请日：2011-09-13
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/28 , H01L21/762
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

28. 发明授权

US08045383B2 Non-volatile memory devices including dummy word lines and related structures and methods 有权
标题翻译：包括虚拟字线和相关结构和方法的非易失性存储器件
公开(公告)号：US08045383B2
公开(公告)日：2011-10-25
申请号：US11729169
申请日：2007-03-28
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Moreover, the first ground select line may be between the second ground select line and the first plurality of word lines, and the second ground select line may be between the first ground select line and the second plurality of word lines. Moreover, portions of the active region between the first and second ground select lines may be free of word lines, and a second spacing between the first and second ground select lines may be at least about 3 times greater than the first spacing. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，有源区上的第一存储单元串和有源区上的第二存储单元串。第一存储单元串可以包括与第一地选择线和第一串选择线之间的有源区域交叉的第一多个字线，并且可以在第一多个字线中相邻的字线之间提供约相同的第一间隔。第二存储单元串可以包括与第二接地选择线和第二串选择线之间的有源区域交叉的第二多个字线，并且可以在相邻的第二多个字线之间提供约相同的第一间隔。此外，第一接地选择线可以在第二接地选择线和第一多个字线之间，并且第二接地选择线可以在第一接地选择线和第二多个字线之间。此外，第一和第二接地选择线之间的有源区域的部分可以没有字线，并且第一和第二接地选择线之间的第二间隔可以比第一间隔大至少约3倍。还讨论了相关方法。

29. 发明授权

US08021978B2 Methods of fabricating flash memory devices having shared sub active regions 有权
标题翻译：制造具有共享子有源区的闪存器件的方法
公开(公告)号：US08021978B2
公开(公告)日：2011-09-20
申请号：US12725936
申请日：2010-03-17
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/44
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

30. 发明授权

US07973354B2 Semiconductor devices with sidewall conductive patterns and methods of fabricating the same 失效
标题翻译：具有侧壁导电图案的半导体器件及其制造方法
公开(公告)号：US07973354B2
公开(公告)日：2011-07-05
申请号：US12133146
申请日：2008-06-04
申请人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
发明人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11529
摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
摘要翻译：公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。下导电图案在基板上。绝缘图案位于下导电图案上。上导电图案位于与下导电图案相对的绝缘图案上。侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。侧壁导电图形电连接上导电图案和下导电图案。下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

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