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21. 发明授权

US5541131A Peeling free metal silicide films using ion implantation 失效
标题翻译：使用离子注入剥离游离金属硅化物膜
公开(公告)号：US5541131A
公开(公告)日：1996-07-30
申请号：US649549
申请日：1991-02-01
申请人： Chue-San Yoo , Ting-Hwang Lin
发明人： Chue-San Yoo , Ting-Hwang Lin
IPC分类号： H01L21/285 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28518 , Y10S148/147
摘要： A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the polycide peeling problems. A pattern of gate electrode structures is formed upon a semiconductor substrate which each includes a gate oxide, a polysilicon layer and an amorphous refractory metal silicide. The resulting structure may be annealed in oxygen at this time to change the refractory metal silicide from it deposited amorphous phase into its crystalline phase. This causes the formation of a thin layer of silicon dioxide upon the exposed silicon substrate, the exposed polysilicon layer and the exposed metal silicide layer. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric layer is blanket deposited over the surfaces and spacer structures formed by anisotropic etching. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The silicon oxide layer on the top surface of the metal silicate layer was removed by etching. Silicon ions are now implanted into the metal silicide layer to supply an excess of silicon ions at the surface of the metal silicide layer. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover.
摘要翻译：描述了一种制造轻掺杂漏极MOSFET集成电路器件的方法，其克服了多晶硅剥离问题。栅电极结构的图案形成在半导体衬底上，每个半导体衬底包括栅极氧化物，多晶硅层和非晶难熔金属硅化物。此时可以在氧气中对所得结构进行退火，以将难熔金属硅化物从其沉积的非晶相变为其结晶相。这导致在暴露的硅衬底，暴露的多晶硅层和暴露的金属硅化物层上形成薄的二氧化硅层。通过使用多晶硅栅极结构作为掩模的离子注入形成衬底中的轻掺杂区域的图案。介电层被覆盖在各个表面上，并通过各向异性蚀刻形成间隔结构。通过使用具有间隔结构的聚硅氧烷结构作为掩模的离子注入形成衬底中的重掺杂区域的图案，以产生MOSFET器件的轻掺杂漏极/漏极结构。通过蚀刻去除金属硅酸盐层的顶表面上的氧化硅层。硅离子现在被注入到金属硅化物层中，以在金属硅化物层的表面处提供过量的硅离子。通过在所描述的结构上形成钝化层并在其上形成适当的电连接结构来完成集成电路器件。

22. 发明授权

US5324689A Critical dimension control with a planarized underlayer 失效
标题翻译：具有平坦化底层的关键尺寸控制
公开(公告)号：US5324689A
公开(公告)日：1994-06-28
申请号：US102976
申请日：1993-07-28
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/44 , H01L21/469
CPC分类号： H01L21/28123 , H01L21/32139
摘要： A new method of controlling the critical dimension width of polysilicon by planarizing the photoresist underlayer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A layer of polysilicon is deposited over the uneven surface of the substrate. The polysilicon layer is covered with a spin-on-glass layer wherein the spin-on-glass material planarizes the surface of the underlying topography. The spin-on-glass layer is covered with a uniform thickness layer of photoresist. The photoresist layer is exposed through the desired mask, developed and patterned to form the desired resist mask. The exposed spin-on-glass and polysilicon layers are removed by etch. The photoresist mask is stripped. The spin-on-glass layer remaining over the polysilicon patterned layer is removed, resulting in the polysilicon layer having the desired uniform critical dimension.
摘要翻译：描述了通过平坦化光致抗蚀剂底层来控制多晶硅的临界尺寸宽度的新方法。提供半导体衬底，其中衬底的表面具有不平坦的形貌。在衬底的不平坦表面上沉积多晶硅层。多晶硅层被旋涂玻璃层覆盖，其中旋涂玻璃材料平坦化底层地形的表面。旋涂玻璃层被均匀厚度的光致抗蚀剂层覆盖。光致抗蚀剂层通过期望的掩模曝光，显影和图案化以形成所需的抗蚀剂掩模。通过蚀刻去除暴露的自旋玻璃和多晶硅层。剥去光致抗蚀剂掩模。残留在多晶硅图案层上的旋涂玻璃层被去除，导致多晶硅层具有所需的均匀临界尺寸。

23. 发明授权

US5268244A Self-aligned phase shifter formation 失效
标题翻译：自对准移相器形成
公开(公告)号：US5268244A
公开(公告)日：1993-12-07
申请号：US929125
申请日：1992-08-13
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： G03F1/29 , G03F9/00
CPC分类号： G03F1/29
摘要： The process of fabricating the phase-shifting photomask includes forming on a substrate a patterned metal layer having vertical and horizontal surfaces. A substantially uniform phase-shifting material is deposited over the patterned metal layer surfaces. The phase-shifting material anisotropically etched to substantially remove the material from the horizontal surfaces and to substantially leave in place the material on the vertical or sidewall surfaces of metal layer to form phase shifter sidewall structures on the vertical or sidewall surfaces to form the phase shifting photomask without use of photoresist lithography in the formation of the phase shifter sidewall structures.
摘要翻译：制造相移光掩模的过程包括在基板上形成具有垂直和水平表面的图案化金属层。在图案化的金属层表面上沉积基本均匀的相移材料。各向异性蚀刻的相移材料基本上从水平表面移除材料并且基本上留下金属层的垂直或侧壁表面上的材料，以在垂直或侧壁表面上形成移相器侧壁结构，以形成相移在不使用光刻胶光刻的光掩模中形成移相器侧壁结构。

24. 发明授权

US5203957A Contact sidewall tapering with argon sputtering 失效
标题翻译：氩气溅射接触侧壁逐渐变细
公开(公告)号：US5203957A
公开(公告)日：1993-04-20
申请号：US713508
申请日：1991-06-12
申请人： Chue-San Yoo , Ting-Hwang Lin , Sui-Hei Kuo
发明人： Chue-San Yoo , Ting-Hwang Lin , Sui-Hei Kuo
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76826 , H01L21/31116 , H01L21/76804
摘要： The method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less is accomplished by first providing an integrated circuit structure having device elements within a semiconductor substate and multilayer insulating layers thereover. A resist masking layer is formed over the multilayer insulating layer having openings therein in the areas where the contact openings are desired. Isotropic etching is done through a desired thickness portion of multilayer insulating layer. Anisotropic etching is now done through the remaining thickness of multilayer insulating layer to the semiconductor substrate to form the desired contact opening. The resist layer is removed. The structure is subjected to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of multilayer layer and the point where the isotropic etching ended and the anisotropic etching began. It is preferred that soft reactive ion etching be done for a period of less than about 30 seconds after said Argon sputter etching to reduce the increased contact resistance caused by this Argon sputter etching.
摘要翻译：通过首先提供具有在半导体子状态内的器件元件和其上的多层绝缘层的集成电路结构，来实现具有约1微米或更小特征尺寸的集成电路的接触开口的方法。在需要接触开口的区域中，在其上具有开口的多层绝缘层上形成抗蚀剂掩模层。通过多层绝缘层的所需厚度部分进行各向同性蚀刻。现在通过多层绝缘层的剩余厚度到半导体衬底来形成各向异性蚀刻以形成所需的接触开口。去除抗蚀剂层。该结构经受氩溅射蚀刻环境以平滑多层层的上表面处的尖角以及各向同性蚀刻结束的点和各向异性蚀刻开始。优选的是，在所述氩溅射蚀刻之后，软反应离子蚀刻进行时间小于约30秒，以减少由该氩溅射蚀刻引起的增加的接触电阻。

25. 发明授权

US06242341B1 Planarization using laser ablation 有权
公开(公告)号：US06242341B1
公开(公告)日：2001-06-05
申请号：US09332423
申请日：1999-06-14
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L2144
CPC分类号： H01L21/7684 , H01L21/76819
摘要： A process for planarization of a silicon wafer is described together with apparatus for implementing it. The process planarizes by directing a high-energy, pulsed laser beam in a direction parallel to the wafer surface while the wafer is rotating. The height of the beam relative to the wafer is carefully controlled thereby enabling the removal of all material above the lower edge of the beam to be removed from the wafer through laser ablation. The method works equally well for removal of metal (as in planarization of damascene wiring) or dielectric (as in planarization of conventional wiring). Once all excess material has been removed (typically requiring about 60 seconds) additional operation of the process does no harm so neither end point detection nor precise control of process time are required.

26. 发明授权

US06200836B1 Using oxide junction to cut off sub-threshold leakage in CMOS devices 有权
标题翻译：使用氧化物结切断CMOS器件中的亚阈值泄漏
公开(公告)号：US06200836B1
公开(公告)日：2001-03-13
申请号：US09368862
申请日：1999-08-06
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L2100
CPC分类号： H01L29/0653 , H01L21/26533
摘要： A new method is provided for the formation of Lightly Doped Drain (LDD) regions in MOS devices. The body of the gate electrode is formed including the self-aligned LDD regions. After the LDD regions have been formed, an oxide implant is performed under an angle into the surface of the substrate on which the MOS device is being formed. This oxide implant forms an oxide layer around the interface between the source/drain regions and the surrounding silicon. The spacers for the gate electrode are formed, the source/drain region implant is completed. This implanted oxygen junction is subjected to a thermal treatment thereby forming an oxide layer around the source/drain regions. This oxide layer eliminates the leakage current across the interface between the source/drain regions and the surrounding silicon further forcing the saturation current between these regions to flow along the surface of the silicon substrate.
摘要翻译：提供了一种在MOS器件中形成轻掺杂漏极（LDD）区域的新方法。形成包括自对准LDD区域的栅电极的主体。在LDD区域形成之后，在其上形成有MOS器件的衬底的表面上以一定角度进行氧化物注入。这种氧化物注入在源/漏区和周围的硅之间的界面周围形成氧化物层。形成用于栅电极的间隔物，完成源极/漏极区域注入。对该注入的氧结进行热处理，从而在源/漏区周围形成氧化物层。该氧化物层消除了源极/漏极区域和周围硅之间的界面处的漏电流，进一步迫使这些区域之间的饱和电流沿着硅衬底的表面流动。

27. 发明授权

US06168984A Reduction of the aspect ratio of deep contact holes for embedded DRAM devices 有权
标题翻译：降低嵌入式DRAM器件深度接触孔的长宽比
公开(公告)号：US06168984A
公开(公告)日：2001-01-02
申请号：US09419103
申请日：1999-10-15
申请人： Chue-San Yoo , Ming-Hsiung Chiang , Wen-Chuan Chiang , Cheng-Ming Wu , Tse-Liang Ying
发明人： Chue-San Yoo , Ming-Hsiung Chiang , Wen-Chuan Chiang , Cheng-Ming Wu , Tse-Liang Ying
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10814 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.
摘要翻译：已经开发了用于在相同的半导体芯片上将用于集成逻辑和DRAM存储器件的厚的绝缘体层中形成的窄直径接触孔的宽高比减小的方法。减小这些接触孔的纵横比的过程，其特征在于，通过图案化步骤，在逻辑区域中最初形成较小的窄直径的接触孔到有源器件区域，同时还形成自对准的接触开口到源极/漏极 DRAM存储区域中的区域。在形成钨结构之后，在下部窄直径的接触孔中，多晶硅位线和多晶硅电容器结构通过上层绝缘体层和多晶硅和多晶硅导电层的沉积和图案形成在DRAM存储区域中。然后在上层绝缘体层中形成上部，小直径的开口，暴露位于下部较窄直径的接触孔中的钨结构的顶表面。在上部窄直径接触开口中形成上部钨结构完成了通过两级接触孔开口形成的具有减小的纵横比的窄直径开口中的金属结构的形成和两阶段金属填充程序的过程。

28. 发明授权

US6025270A Planarization process using tailored etchback and CMP 失效
标题翻译：使用定制回蚀和CMP的平面化过程
公开(公告)号：US6025270A
公开(公告)日：2000-02-15
申请号：US794693
申请日：1997-02-03
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/3105 , H01L21/302
CPC分类号： H01L21/31056 , H01L21/31053
摘要： An improved and new method for forming a planarized integrated cirsuit structure has been developed. The method uses a combination of etchback and chemical/mechanical polishing (CMP), in which the etchback process uses a tailored mask to compensate for non-unifomity of material removal by the subsequent chemical/mechanical (CMP) process, thereby resulting in improved planarization and superior thickness uniformity.
摘要翻译：已经开发了一种形成平面化的集成连接结构的改进和新的方法。该方法使用回蚀和化学/机械抛光（CMP）的组合，其中回蚀工艺使用定制的掩模来补偿随后的化学/机械（CMP）工艺去除材料的非一体性，从而导致改进的平坦化并具有优异的厚度均匀性。

29. 发明授权

US06177340B1 Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure 有权
标题翻译：通过使用钨位线结构来减少嵌入式DRAM阵列和逻辑器件的接触孔纵横比的方法
公开(公告)号：US06177340B1
公开(公告)日：2001-01-23
申请号：US09252470
申请日：1999-02-18
申请人： Chue-San Yoo , Chen Jong Wang , Wen Chuan Chiang
发明人： Chue-San Yoo , Chen Jong Wang , Wen Chuan Chiang
IPC分类号： H01L214763
CPC分类号： H01L21/76877 , H01L21/31116 , H01L21/76816 , H01L27/10855 , H01L27/10888 , H01L27/10897
摘要： A method for reducing the high aspect ratios, encountered when forming, and filling, narrow diameter contact holes, in thick insulator layers, has been developed, featuring a two step contact hole opening and filling procedure. First, lower narrow diameter contact holes are opened in lower levels of insulator layers, then filled with tungsten. After deposition of upper levels of insulator layers, upper narrow diameter contact holes are formed, exposing the tungsten filled, lower diameter contact holes. A second tungsten layer fills the upper, narrow diameter contact hole, resulting in a final narrow diameter contact hole, in thick insulator layers, formed with reduced aspect ratios, via use of the two contact hole openings, and the two tungsten fill procedures. In addition these procedures allow a damascene, tungsten bit line structure, to be formed in a dual shaped opening, in lower insulator layers.
摘要翻译：已经开发了一种用于减小在厚的绝缘体层中形成和填充窄直径接触孔时遇到的高纵横比的方法，具有两步接触孔打开和填充程序。首先，较低的直径的接触孔在较低级别的绝缘体层中打开，然后用钨填充。在沉积上层绝缘体层之后，形成上部窄径接触孔，暴露出填充钨的较小直径的接触孔。第二钨层填充上部较窄直径的接触孔，通过使用两个接触孔开口和两个钨填充程序，在较厚的绝缘体层中形成具有减小的纵横比的最终窄直径的接触孔。此外，这些方法允许在下绝缘体层中形成镶嵌钨丝线结构的双面形开口。

30. 发明授权

US06054368A Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages 失效
公开(公告)号：US06054368A
公开(公告)日：2000-04-25
申请号：US884914
申请日：1997-06-30
申请人： Chue-San Yoo , Cheng-Yeh Shih
发明人： Chue-San Yoo , Cheng-Yeh Shih
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/32
摘要： A method and structure for forming a modified field oxide region having increased field oxide threshold voltages (V.sub.th) and/or reduced leakage currents between adjacent device areas is achieved. The method involves forming a field oxide using the conventional local oxidation of silicon (LOCOS) using a patterned silicon nitride layer as a barrier to oxidation. After forming the LOCOS field oxide by thermal oxidation and removing the silicon nitride, a conformal insulating layer composed of silicon oxide is deposited and anisotropically etched back to form sidewall insulating portions over the bird's beak on the edge of the LOCOS field oxide, thereby forming a new modified field oxide. P-channel implants are formed in the device areas. Then a second implant is used to implant through the modified field oxide to provide channel-stop regions with modified profiles that increase the field oxide V.sub.th and/or reduce leakage current between device areas. This improved field oxide/channel-stop structure is particularly useful for reducing the leakage current on DRAM cells thereby increasing the refresh cycle times.

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