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21. 发明申请

US20120205737A1 SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION 有权
标题翻译： SHIELDED GATE TRENCH MOSFET器件和制造
公开(公告)号：US20120205737A1
公开(公告)日：2012-08-16
申请号：US13456406
申请日：2012-04-26
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

22. 发明申请

US20120187472A1 TRENCH POLY ESD FORMATION FOR TRENCH MOS AND SGT 有权
标题翻译： TRENCH MOS和SGT的TRENCH POLY ESD形成
公开(公告)号：US20120187472A1
公开(公告)日：2012-07-26
申请号：US13010427
申请日：2011-01-20
申请人： Hong Chang , John Chen
发明人： Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7393 , H01L27/0259 , H01L29/7827
摘要： A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P—N—P or N—P—N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.
摘要翻译：描述半导体器件及其制造方法。形成在半导体衬底中的沟槽部分地填充所述沟槽，其中半导体材料对沟槽的底部和侧面进行排列，在沟槽的中间留下间隙，沿沟槽沿纵向延伸。位于间隙下方的半导体材料的第一部分掺杂有第一导电类型的掺杂剂。间隙填充有电介质材料。位于电介质材料两侧的沟槽侧面的半导体材料的第二部分掺杂有第二导电类型的掺杂剂。掺杂形成沿着沟槽纵向延伸的P-N-P或N-P-N结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。

23. 发明授权

US08193580B2 Shielded gate trench MOSFET device and fabrication 有权
标题翻译：屏蔽栅沟槽MOSFET器件和制造
公开(公告)号：US08193580B2
公开(公告)日：2012-06-05
申请号：US12583191
申请日：2009-08-14
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

24. 发明申请

US20110316076A1 Power MOSFET Device with Self-Aligned Integrated Schottky and its Manufacturing Method 有权
标题翻译：具有自对准集成肖特基的功率MOSFET器件及其制造方法
公开(公告)号：US20110316076A1
公开(公告)日：2011-12-29
申请号：US12826591
申请日：2010-06-29
申请人： Yeeheng Lee , Yongping Ding , John Chen
发明人： Yeeheng Lee , Yongping Ding , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/782
摘要： A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.
摘要翻译：功率MOSFET器件及其制造方法包括以下步骤：在接触沟槽的底部的中间区域选择性地沉积第一导电材料，并与光掺杂的N型外延层接触以形成肖特基结，并沉积第二导电材料导电材料在接触沟槽的侧壁和底角处并与P型重掺杂体区域接触以形成欧姆结。第一和第二导电材料可以分别优化欧姆接触和肖特基接触的性能而不折不扣。同时，接触沟槽的角部被P型重掺杂区域围绕，从而有效地减少了在接触沟槽的拐角处积聚的漏电流。

25. 发明申请

US20110220990A1 SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT 有权
标题翻译： SHIELDED GATE TRENCH MOS与改进的来源PICKUP布局
公开(公告)号：US20110220990A1
公开(公告)日：2011-09-15
申请号：US12722384
申请日：2010-03-11
申请人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
发明人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/283 , H01L27/088 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
摘要翻译：一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。使用第二掩模形成由中间介电区分隔的第一和第二导电区域。使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。使用第四掩模形成与栅极金属区域的接触。半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

26. 发明申请

US20110147830A1 METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS 有权
标题翻译：形成自对准电荷平衡功率DMOS的方法
公开(公告)号：US20110147830A1
公开(公告)日：2011-06-23
申请号：US12643837
申请日：2009-12-21
申请人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Yeeheng Lee , Lingpeng Guan , Moses Ho , Wilson Ma , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/165 , H01L29/456 , H01L29/66719 , H01L29/78 , H01L29/7811
摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.
摘要翻译：公开了自对准电荷平衡半导体器件及其形成方法。在第一导电类型的半导体衬底上形成一个或多个平面栅极。在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

27. 发明申请

US20110143512A1 METHOD FOR DUAL ENERGY IMPLANTATION FOR ULTRA-SHALLOW JUNCTION FORMATION OF MOS DEVICES 有权
标题翻译：用于双能量植入的方法，用于超微结构形成MOS器件
公开(公告)号：US20110143512A1
公开(公告)日：2011-06-16
申请号：US12830241
申请日：2010-07-02
申请人： HANMING WU , Chia Hao Lee , John Chen
发明人： HANMING WU , Chia Hao Lee , John Chen
IPC分类号： H01L21/336 , H01L21/265 , H01J1/50
CPC分类号： H01J37/3171 , H01J37/3007 , H01J2237/055 , H01J2237/0825 , H01L21/2236 , H01L21/26513 , H01L29/0847 , H01L29/6659 , H01L29/7833
摘要： A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).
摘要翻译：一种在半导体衬底中形成轻掺杂漏极（LDD）区域的方法。该方法包括产生所选物种的离子束并加速离子束，其中加速离子束包括第一加速部分和第二加速部分。该方法还包括偏转加速离子束，其中第一和第二加速部分同时偏转到具有第一偏转角的第一路径轨迹和具有第二偏转角的第二路径轨迹。在一个实施例中，第一和第二路径轨迹在与半导体晶片的表面区域垂直的相同方向上行进，并且第一偏转角度大于第二偏转角度。在一个实施方案中，所选择的物质可以包括包含磷（P），砷（As）或锑（Sb）的n型离子。

28. 发明申请

US20110039383A1 Shielded gate trench MOSFET device and fabrication 有权
标题翻译：屏蔽栅沟槽MOSFET器件和制造
公开(公告)号：US20110039383A1
公开(公告)日：2011-02-17
申请号：US12583192
申请日：2009-08-14
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.
摘要翻译：一种制造半导体器件的方法包括形成多个沟槽，包括施加第一掩模，在多个沟槽中的至少一些沟槽中形成第一多晶硅区域，形成多晶硅间介质区域和端接保护区域，包括施加第二掩模，在所述多个沟槽中的所述至少一些沟槽中形成第二多晶硅区域，形成到所述第一多晶硅区域的第一电接触并且形成到所述第二多晶硅区域的第二电接触，包括施加第三掩模，金属层，并且形成源极金属区域和栅极金属区域，包括施加第四掩模。

29. 发明授权

US07879676B2 High density trench mosfet with single mask pre-defined gate and contact trenches 有权
标题翻译：高密度沟槽mosfet与单一掩模预定义的门和接触沟槽
公开(公告)号：US07879676B2
公开(公告)日：2011-02-01
申请号：US12847863
申请日：2010-07-30
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

30. 发明授权

US07717749B2 Multiport RJ connector 有权
标题翻译：多端RJ连接器
公开(公告)号：US07717749B2
公开(公告)日：2010-05-18
申请号：US10657343
申请日：2003-09-08
申请人： John Chen , Kwok Fai Lai , Kuok Sang Leong , Man Tat Yip , Wai Shun Leung , Chun Wing Ng , Quincy Lee
发明人： John Chen , Kwok Fai Lai , Kuok Sang Leong , Man Tat Yip , Wai Shun Leung , Chun Wing Ng , Quincy Lee
IPC分类号： H01R13/68
CPC分类号： H01R13/6658 , H01R24/64
摘要： A multiport connector which includes a housing having at least two aligned compartments, each compartment being structured and arranged to receive respective plugs. A multilayer printed wiring board separates the two compartments, the printed wiring board having circuit patterns on opposite sides of opposed non-conductive layers and a metal shielding layer intermediate the non-conductive layers. A first plurality of conductive contact fingers is disposed in one of the compartments, the first plurality of fingers having first portions for making electrical contact with one of the plugs and second portions for making contact with the circuit pattern on one of the non-conductive layers of the multilayer printed wiring board. A second plurality of conductive contact fingers is disposed in the other of the compartments, the second plurality of fingers having first portions for making electrical contact with the other one of the plugs and second portions for making contact with the circuit pattern on the other one of the non-conductive layers of the multilayer printed wiring board.
摘要翻译：一种多端口连接器，其包括具有至少两个对准隔室的壳体，每个隔室被构造和布置成接收相应的插头。多层印刷线路板将两个隔室，具有相对的非导电层的相对侧上的电路图案的印刷电路板和在非导电层之间的金属屏蔽层分离。第一多个导电接触指状物设置在其中一个隔室中，第一多个指状物具有用于与塞子中的一个电气接触的第一部分和用于与电路图案在非导电层之一接触的第二部分的多层印刷线路板。第二多个导电接触指状物设置在另一个隔间中，第二多个指状物具有用于与另一个插塞和第二部分电接触的第一部分，用于与另一个上的电路图案接触多层印刷线路板的非导电层。

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