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1. 发明授权

US08847306B2 Direct contact in trench with three-mask shield gate process 有权
标题翻译：直接接触沟槽与三屏蔽屏蔽门工艺
公开(公告)号：US08847306B2
公开(公告)日：2014-09-30
申请号：US13343666
申请日：2012-01-04
申请人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
发明人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
IPC分类号： H01L29/66 , H01L21/336 , H01L29/423 , H01L29/78 , H01L29/40 , H01L29/45 , H01L29/49 , H01L29/08 , H01L21/265
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。第一导电材料形成在沟槽的底部。在第一导电材料上方形成由绝缘体隔开的第二导电材料。在沟槽上形成第一绝缘体层。在衬底中形成体层。源体形成在体层中。在沟槽和源极上形成第二绝缘体层。源极和栅极触点通过第二绝缘体层形成。源极和栅极金属形成在第二绝缘体层上。提供该摘要以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

2. 发明授权

US08772828B2 Trench poly ESD formation for trench MOS and SGT 有权
标题翻译：沟槽MOS和SGT的沟槽聚合物ESD形成
公开(公告)号：US08772828B2
公开(公告)日：2014-07-08
申请号：US13911871
申请日：2013-06-06
申请人： Hong Chang , John Chen
发明人： Hong Chang , John Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7393 , H01L27/0259 , H01L29/7827
摘要： A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：半导体器件包括设置在具有至少沟槽底部的多晶硅衬底的沟槽中的半导体材料。半导体材料包括不同的掺杂区域，其被配置为在沟槽中形成的PNP或NPN结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

3. 发明申请

US20120205737A1 SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION 有权
标题翻译： SHIELDED GATE TRENCH MOSFET器件和制造
公开(公告)号：US20120205737A1
公开(公告)日：2012-08-16
申请号：US13456406
申请日：2012-04-26
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

4. 发明申请

US20120187472A1 TRENCH POLY ESD FORMATION FOR TRENCH MOS AND SGT 有权
标题翻译： TRENCH MOS和SGT的TRENCH POLY ESD形成
公开(公告)号：US20120187472A1
公开(公告)日：2012-07-26
申请号：US13010427
申请日：2011-01-20
申请人： Hong Chang , John Chen
发明人： Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7393 , H01L27/0259 , H01L29/7827
摘要： A semiconductor device and its method of fabrication are described. A trench formed in a semiconductor substrate is partially filling said trench with a semiconductor material that lines a bottom and sides of the trench, leaving a gap in a middle of the trench running lengthwise along the trench. A first portion of the semiconductor material located below the gap is doped with dopants of a first conductivity type. The gap is filled with a dielectric material. Second portions of the semiconductor material located on the sides of the trench on both sides of the dielectric material are doped with dopants of a second conductivity type. The doping forms a P—N—P or N—P—N structure running lengthwise along the trench with differently doped regions located side by side across a width of the trench.
摘要翻译：描述半导体器件及其制造方法。形成在半导体衬底中的沟槽部分地填充所述沟槽，其中半导体材料对沟槽的底部和侧面进行排列，在沟槽的中间留下间隙，沿沟槽沿纵向延伸。位于间隙下方的半导体材料的第一部分掺杂有第一导电类型的掺杂剂。间隙填充有电介质材料。位于电介质材料两侧的沟槽侧面的半导体材料的第二部分掺杂有第二导电类型的掺杂剂。掺杂形成沿着沟槽纵向延伸的P-N-P或N-P-N结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。

5. 发明授权

US08193580B2 Shielded gate trench MOSFET device and fabrication 有权
标题翻译：屏蔽栅沟槽MOSFET器件和制造
公开(公告)号：US08193580B2
公开(公告)日：2012-06-05
申请号：US12583191
申请日：2009-08-14
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
摘要翻译：半导体器件实施例包括衬底，衬底中的有源栅极沟槽和衬底中的不对称沟槽。非对称沟槽具有第一沟槽壁和第二沟槽壁，第一沟槽壁衬有具有第一厚度的氧化物，并且第二沟槽壁衬有具有不同于第一厚度的第二厚度的氧化物。另一半导体器件实施例包括衬底，衬底中的有源栅极沟槽; 以及衬底中的源极多晶硅拾取沟槽。源多晶硅拾取沟槽包括多晶硅电极，并且多晶硅电极的顶表面在身体区域的底部之下。另一个半导体器件包括衬底，衬底中的有源栅极沟槽，有源栅极沟槽具有第一顶部栅电极和第一底部源极电极，以及包括第二顶部栅电极和第二底部源极电极的栅极流道沟槽。第二顶栅电极比第二底源电极窄。

6. 发明申请

US20110220990A1 SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT 有权
标题翻译： SHIELDED GATE TRENCH MOS与改进的来源PICKUP布局
公开(公告)号：US20110220990A1
公开(公告)日：2011-09-15
申请号：US12722384
申请日：2010-03-11
申请人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
发明人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/283 , H01L27/088 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
摘要翻译：一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。使用第二掩模形成由中间介电区分隔的第一和第二导电区域。使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。使用第四掩模形成与栅极金属区域的接触。半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

7. 发明申请

US20110039383A1 Shielded gate trench MOSFET device and fabrication 有权
标题翻译：屏蔽栅沟槽MOSFET器件和制造
公开(公告)号：US20110039383A1
公开(公告)日：2011-02-17
申请号：US12583192
申请日：2009-08-14
申请人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
发明人： John Chen , Il Kwan Lee , Hong Chang , Wenjun Li , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.
摘要翻译：一种制造半导体器件的方法包括形成多个沟槽，包括施加第一掩模，在多个沟槽中的至少一些沟槽中形成第一多晶硅区域，形成多晶硅间介质区域和端接保护区域，包括施加第二掩模，在所述多个沟槽中的所述至少一些沟槽中形成第二多晶硅区域，形成到所述第一多晶硅区域的第一电接触并且形成到所述第二多晶硅区域的第二电接触，包括施加第三掩模，金属层，并且形成源极金属区域和栅极金属区域，包括施加第四掩模。

8. 发明授权

US07879676B2 High density trench mosfet with single mask pre-defined gate and contact trenches 有权
标题翻译：高密度沟槽mosfet与单一掩模预定义的门和接触沟槽
公开(公告)号：US07879676B2
公开(公告)日：2011-02-01
申请号：US12847863
申请日：2010-07-30
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

9. 发明授权

US09887283B2 Process method and structure for high voltage MOSFETs 有权
公开(公告)号：US09887283B2
公开(公告)日：2018-02-06
申请号：US13892191
申请日：2013-05-10
申请人： Yongping Ding , Lei Zhang , Hong Chang , Jongoh Kim , John Chen
发明人： Yongping Ding , Lei Zhang , Hong Chang , Jongoh Kim , John Chen
IPC分类号： H01L29/78 , H01L29/66 , H01L21/265
CPC分类号： H01L29/78 , H01L21/2652 , H01L21/26586 , H01L29/66348 , H01L29/66666 , H01L29/7827
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

10. 发明授权

US08580676B2 Multiple layer barrier metal for device component formed in contact trench 有权
标题翻译：用于器件部件的多层阻挡金属形成在接触沟槽中
公开(公告)号：US08580676B2
公开(公告)日：2013-11-12
申请号：US13361486
申请日：2012-01-30
申请人： Hong Chang , John Chen , Limin Weng , Wenjun Li
发明人： Hong Chang , John Chen , Limin Weng , Wenjun Li
IPC分类号： H01L21/4763
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/782 , H01L2924/0002 , Y10S257/905 , H01L2924/00
摘要： A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.
摘要翻译：形成在半导体衬底上的半导体器件可以包括形成在位于活性单元区域中的接触沟槽中的部件。该部件可以包括沉积在接触沟槽的底部和侧壁的一部分上的阻挡金属和沉积在接触沟槽的剩余部分中的钨丝塞。阻挡金属可以包括第一和第二金属层。第一金属层可以靠近接触沟槽的侧壁和底部。第一金属层可以包括氮化物。第二金属层可以在第一金属层和钨插塞之间以及钨插塞和侧壁之间。第二金属层覆盖未被第一金属层覆盖的侧壁的部分。

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