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21. 发明授权

US06479368B1 Method of manufacturing a semiconductor device having a shallow trench isolating region 失效
标题翻译：制造具有浅沟槽隔离区域的半导体器件的方法
公开(公告)号：US06479368B1
公开(公告)日：2002-11-12
申请号：US09033067
申请日：1998-03-02
申请人： Jack A. Mandelman , Mutsuo Morikado , Herbert Ho , Jeffrey P. Gambino
发明人： Jack A. Mandelman , Mutsuo Morikado , Herbert Ho , Jeffrey P. Gambino
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of manufacturing a semiconductor device, in which the depth of a divot in a shallow trench isolation can be decreased. The method comprises forming a trench in a semiconductor substrate, for isolating elements, forming a nitride film on a surface of the trench, depositing mask material on an entire surface of the semiconductor substrate, filling the trench with the mask material, etching the mask material until a surface level of the mask material in the trench falls below the surface of the semiconductor substrate, removing an exposed upper portion of the nitride film on the surface of the trench, removing the mask material from the trench, filling the trench with element-isolating material, thereby forming an element-isolating region, and forming a transistor in an element region isolated from another element region by the element-isolating region.
摘要翻译：一种制造半导体器件的方法，其中可以减少浅沟槽隔离中的凹陷的深度。该方法包括在半导体衬底中形成沟槽，用于隔离元件，在沟槽的表面上形成氮化物膜，在半导体衬底的整个表面上沉积掩模材料，用掩模材料填充沟槽，蚀刻掩模材料直到沟槽中的掩模材料的表面水平落在半导体衬底的表面之下，去除沟槽表面上暴露的氮化物膜的上部，从沟槽中去除掩模材料，从而形成元件隔离区域，并且通过元件隔离区域在与另一个元件区域隔离的元件区域中形成晶体管。

22. 发明授权

US06350653B1 Embedded DRAM on silicon-on-insulator substrate 有权
标题翻译：绝缘体上硅衬底上的嵌入式DRAM
公开(公告)号：US06350653B1
公开(公告)日：2002-02-26
申请号：US09689096
申请日：2000-10-12
申请人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
发明人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
摘要翻译：提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中，其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。还公开了所得到的结构。

23. 发明授权

US6090671A Reduction of gate-induced drain leakage in semiconductor devices 失效
标题翻译：降低半导体器件中的栅极漏极泄漏
公开(公告)号：US6090671A
公开(公告)日：2000-07-18
申请号：US941600
申请日：1997-09-30
申请人： Karanam Balasubramanyam , Martin Gall , Jeffrey P. Gambino , Jack A. Mandelman
发明人： Karanam Balasubramanyam , Martin Gall , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L21/26 , H01L21/28 , H01L21/324 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28176 , H01L21/324 , H01L27/10873 , Y10S438/91
摘要： Reduction of gate-induced-drain-leakage in metal oxide semiconductor (MOS) devices is achieved by performing an anneal in a non-oxidizing ambient. In one embodiment, the anneal is performed in a argon and/or ammonia ambients after gate sidewall oxidation that forms the spacers.
摘要翻译：通过在非氧化性环境中进行退火来实现金属氧化物半导体（MOS）器件中栅极引起的漏极泄漏的减少。在一个实施例中，在形成间隔物的栅极侧壁氧化之后，在氩气和/或氨气氛中进行退火。

24. 发明授权

US06429474B1 Storage-capacitor electrode and interconnect 失效
标题翻译：储存电容电极和互连
公开(公告)号：US06429474B1
公开(公告)日：2002-08-06
申请号：US09547335
申请日：2000-04-11
申请人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
发明人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L23/522 , H01L27/10894 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括与存储电容器的各个板同时形成的下电容器电极和上电容器电极。两个电容器电极可用于在DRAM单元阵列内形成不同的互连。

25. 发明授权

US06395594B2 Method for simultaneously forming a storage-capacitor electrode and interconnect 失效
标题翻译：同时形成储存电容电极和互连的方法
公开(公告)号：US06395594B2
公开(公告)日：2002-05-28
申请号：US09750790
申请日：2001-01-02
申请人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
发明人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10882 , H01L27/10894
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括用于制造两种类型互连的至少一个并且优选两个电容器电极。制造DRAM存储单元的方法包括：形成一个或多个电容电极，同时形成存储单元的存储电容器的电极，以及与辅助电容器电极相同的材料。

26. 发明授权

US06426247B1 Low bitline capacitance structure and method of making same 失效
标题翻译：低位线电容结构及其制作方法
公开(公告)号：US06426247B1
公开(公告)日：2002-07-30
申请号：US09764824
申请日：2001-01-17
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L21338
CPC分类号： H01L27/10888 , H01L23/485 , H01L27/10861 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness ranging from about 100 to about 400 angstroms; and, depositing and planarizing a layer of polysilicon covering said gate structure and the sidewall spacers.
摘要翻译：一种用于形成具有低位线电容的存储器件的方法，包括：在硅衬底上提供栅极导体堆叠结构，所述栅堆叠结构具有栅极氧化层，多晶硅层，硅化物层和顶部电介质氮化物层; 氧化所述栅极氧化层的侧壁; 在所述栅极导体堆叠的侧壁上形成侧壁间隔物，所述侧壁间隔物包括厚度范围为约50至约250埃的薄氮化物层; 用具有约25至约150埃的厚度的薄氮化物衬垫覆盖栅极结构; 在栅极结构上沉积绝缘氧化物层; 将绝缘氧化物层抛光到栅极结构的氮化物衬垫的水平面; 图案化和蚀刻绝缘氧化物层以暴露所述氮化物衬垫; 在所述第一侧壁间隔物上形成第二侧壁间隔物，所述第二侧壁间隔物包括厚度范围为约100至约400埃的氧化物层; 并且沉积和平坦化覆盖所述栅极结构和侧壁间隔物的多晶硅层。

27. 发明授权

US6060746A Power transistor having vertical FETs and method for making same 失效
标题翻译：具有垂直FET的功率晶体管及其制造方法
公开(公告)号：US6060746A
公开(公告)日：2000-05-09
申请号：US798663
申请日：1997-02-11
申请人： Claude L. Bertin , Jeffrey P. Gambino , Jack A. Mandelman
发明人： Claude L. Bertin , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A power transistor having of a plurality of vertical MOSFET devices combined in parallel to achieve high-performance operation and methods of fabricating this device.
摘要翻译：具有并联组合的多个垂直MOSFET器件以实现高性能操作的功率晶体管和制造该器件的方法。

28. 发明授权

US6037648A Semiconductor structure including a conductive fuse and process for fabrication thereof 失效
标题翻译：包括导电熔丝的半导体结构及其制造方法
公开(公告)号：US6037648A
公开(公告)日：2000-03-14
申请号：US105647
申请日：1998-06-26
申请人： Kenneth C. Arndt , Jeffrey P. Gambino , Jack A. Mandelman , Chandrasekhar Narayan , Rainer F. Schnabel , Ronald J. Schutz , Dirk Tobben
发明人： Kenneth C. Arndt , Jeffrey P. Gambino , Jack A. Mandelman , Chandrasekhar Narayan , Rainer F. Schnabel , Ronald J. Schutz , Dirk Tobben
IPC分类号： H01L21/82 , H01L21/768 , H01L23/525 , H01L29/00
CPC分类号： H01L21/76885 , H01L23/5256 , H01L2924/0002
摘要： A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.
摘要翻译：包括半导体衬底的半导体结构，衬底上的导电电平和位于导电水平处的金属熔断器，其中熔丝包括其上的自对准电介质蚀刻停止层以及其制造工艺。

29. 发明授权

US06344389B1 Self-aligned damascene interconnect 有权
公开(公告)号：US06344389B1
公开(公告)日：2002-02-05
申请号：US09294076
申请日：1999-04-19
申请人： Gary B. Bronner , Jeffrey P. Gambino , Carl J. Radens
发明人： Gary B. Bronner , Jeffrey P. Gambino , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： A structure and method for a capacitor-over-bitline integrated circuit device includes forming a device on a substrate, forming a capacitor contact electrically connected to the device, forming a bitline trench using the capacitor contact to align the bitline trench, forming insulating spacers in the bitline trench, forming a conductive bitline in the trench, the bitline being electrically connected to the device, forming an inter-layer dielectric over the bitline, and forming a capacitor above the inter-layer dielectric, such that the capacitor is electrically connected to the capacitor contact.

30. 发明授权

US06201272B1 Method for simultaneously forming a storage-capacitor electrode and interconnect 失效
公开(公告)号：US06201272B1
公开(公告)日：2001-03-13
申请号：US09300899
申请日：1999-04-28
申请人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
发明人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
IPC分类号： H01L27108
CPC分类号： H01L27/10882 , H01L27/10894
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.

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