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21. 发明授权

US06465830B2 RF voltage controlled capacitor on thick-film SOI 有权
标题翻译：射频压控电容器在厚膜SOI上
公开(公告)号：US06465830B2
公开(公告)日：2002-10-15
申请号：US09862775
申请日：2001-05-21
申请人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto
发明人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto
IPC分类号： H01L31119
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/93
摘要： A voltage controlled capacitor sandwiched between a buried oxide and a shallow trench insulator to form a near ideal P+ to n-well diode with minimal parasitic capacitance and resistance.
摘要翻译：一个夹在埋氧层和浅沟槽绝缘子之间的压控电容器，以最小的寄生电容和电阻形成一个接近理想的P +到n-阱二极管。

22. 发明申请

US20110111553A1 ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS 有权
标题翻译：高级CMOS使用超级梯形变压器
公开(公告)号：US20110111553A1
公开(公告)日：2011-05-12
申请号：US13006224
申请日：2011-01-13
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L51/40
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

23. 发明授权

US07883977B2 Advanced CMOS using super steep retrograde wells 有权
标题翻译：先进的CMOS使用超级陡逆流井
公开(公告)号：US07883977B2
公开(公告)日：2011-02-08
申请号：US12356371
申请日：2009-01-20
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

24. 发明申请

US20080132012A1 Advanced CMOS Using Super Steep Retrograde Wells 有权
标题翻译：高级CMOS使用超级陡逆行井
公开(公告)号：US20080132012A1
公开(公告)日：2008-06-05
申请号：US11928652
申请日：2007-10-30
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L21/8238
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

25. 发明授权

US06958523B2 On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits 有权
标题翻译：片上加热用于多晶硅和多晶硅 - 锗 - 锗电阻器的电气修整和用于集成电路的电可编程保险丝
公开(公告)号：US06958523B2
公开(公告)日：2005-10-25
申请号：US09949541
申请日：2001-09-07
申请人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard , Philipp Steinmann , Scott Balster
发明人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard , Philipp Steinmann , Scott Balster
IPC分类号： H01C7/13 , H01C17/26 , H01L23/34 , H01L27/08 , H01L29/00
CPC分类号： H01L27/0802 , H01C7/13 , H01C17/267 , H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.
摘要翻译：形成用于使用微调电阻器和/或可编程保险丝的集成电路可编程结构（60）。可编程结构包括将加热元件（70）放置在可编程结构（60）附近以在编程期间加热可编程结构（60）。

26. 发明授权

US06794237B2 Lateral heterojunction bipolar transistor 有权
公开(公告)号：US06794237B2
公开(公告)日：2004-09-21
申请号：US10313349
申请日：2002-12-06
申请人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard
IPC分类号： H01L21331
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42304 , H01L29/7317
摘要： A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20), and intrinsic emitter region (25) are formed in the thin film silicon layer (6) overlying the buried insulator layer (4). A base electrode (10) is formed of polysilicon, and has a polysilicon filament (10f) that extends over the edge of an insulator layer (8) to contact the silicon layer (6). After formation of insulator filaments (12) along the edges of the base electrode (10) and insulator layer (8), the thin film silicon layer (6) is etched through, exposing an edge. An angled ion implantation then implants the heterojunction species, for example germanium and carbon, into the exposed edge of the thin film silicon layer (6), which after anneal forms the heterojunction base region (20). Polysilicon plugs for the emitter (24e) and collector (24c) are then formed, from which dopant diffuses to form the intrinsic emitter (25) and subcollector (22) of the device.

27. 发明申请

US20120164802A1 ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS 有权
标题翻译：高级CMOS使用超级梯形变压器
公开(公告)号：US20120164802A1
公开(公告)日：2012-06-28
申请号：US13359125
申请日：2012-01-26
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

28. 发明授权

US07199430B2 Advanced CMOS using super steep retrograde wells 有权
标题翻译：先进的CMOS使用超级陡逆流井
公开(公告)号：US07199430B2
公开(公告)日：2007-04-03
申请号：US11362908
申请日：2006-02-28
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

29. 发明授权

US06927428B2 Lateral heterojunction bipolar transistor 有权
标题翻译：横向异质结双极晶体管
公开(公告)号：US06927428B2
公开(公告)日：2005-08-09
申请号：US10818931
申请日：2004-04-06
申请人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard
IPC分类号： H01L21/84 , H01L27/12 , H01L29/423 , H01L29/73 , H01L29/737
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42304 , H01L29/7317
摘要： A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20), and intrinsic emitter region (25) are formed in the thin film silicon layer (6) overlying the buried insulator layer (4). A base electrode (10) is formed of polysilicon, and has a polysilicon filament (10f) that extends over the edge of an insulator layer (8) to contact the silicon layer (6). After formation of insulator filaments (12) along the edges of the base electrode (10) and insulator layer (8), the thin film silicon layer (6) is etched through, exposing an edge. An angled ion implantation then implants the heterojunction species, for example germanium and carbon, into the exposed edge of the thin film silicon layer (6), which after anneal forms the heterojunction base region (20). Polysilicon plugs for the emitter (24e) and collector (24c) are then formed, from which dopant diffuses to form the intrinsic emitter (25) and subcollector (22) of the device.
摘要翻译：公开了一种绝缘体上硅（SOI）结构中的异质结双极晶体管（30）。在覆盖在掩埋绝缘体层（4）上的薄膜硅层（6）中形成晶体管集电极（28），异质结基极区（20）和本征发射极区（25）。基极（10）由多晶硅形成，并且具有在绝缘体层（8）的边缘上延伸以接触硅层（6）的多晶硅细丝（10f）。沿着基极（10）和绝缘体层（8）的边缘形成绝缘体细丝（12）之后，将薄膜硅层（6）蚀刻通过边缘露出。然后，成角度的离子注入将异质结物质（例如锗和碳）注入到薄膜硅层（6）的暴露边缘中，其在退火后形成异质结基极区域（20）。然后形成用于发射极（24e）和集电极（24c）的多晶硅插头，掺杂剂从该多晶硅插塞扩散以形成器件的本征发射极（25）和子集电极（22）。

30. 发明申请

US20050098093A1 Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer 有权
标题翻译：制造外延硅锗层的方法和包括外延砷原位掺杂硅 - 锗层的集成半导体器件
公开(公告)号：US20050098093A1
公开(公告)日：2005-05-12
申请号：US10934188
申请日：2004-09-02
申请人： Jeffrey Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
发明人： Jeffrey Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
IPC分类号： C23C16/42 , C23C16/56 , C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14 , H01L21/205 , H01L21/331 , H01L21/8222 , H01L29/737
CPC分类号： C23C16/42 , C23C16/56 , H01L21/02532 , H01L21/02576
摘要： A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.
摘要翻译：制造用于集成半导体器件的外延硅 - 锗层的方法包括沉积砷原位掺杂硅 - 锗层的步骤，其中砷和锗随后在沉积期间被引入所述硅 - 锗层的不同区域所述硅 - 锗层。通过从锗中分离砷，可避免在沉积过程中砷和锗之间的相互作用，从而允许制造具有可重复掺杂分布的硅 - 锗层。

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