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21. 发明授权

US07494748B2 Method for correction of defects in lithography masks 失效
标题翻译：光刻掩模中缺陷校正方法
公开(公告)号：US07494748B2
公开(公告)日：2009-02-24
申请号：US10904308
申请日：2004-11-03
申请人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
发明人： James W. Adkisson , Eric M. Coker , Christopher K. Magg , Jed H. Rankin , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/72 , G03F1/70
摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.
摘要翻译：用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

22. 发明申请

US20080272399A1 PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES 有权
公开(公告)号：US20080272399A1
公开(公告)日：2008-11-06
申请号：US12172305
申请日：2008-07-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Loiseau
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281
摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

23. 发明申请

US20080116537A1 CMOS IMAGER ARRAY WITH RECESSED DIELECTRIC 有权
标题翻译： CMOS图像阵列带有电介质
公开(公告)号：US20080116537A1
公开(公告)日：2008-05-22
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/146 , H01L21/04
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。

24. 发明申请

US20080029844A1 ANTI-FUSE STRUCTURE OPTIONALLY INTEGRATED WITH GUARD RING STRUCTURE 审中-公开
标题翻译：防腐结构选择性地与保护环结构集成
公开(公告)号：US20080029844A1
公开(公告)日：2008-02-07
申请号：US11462070
申请日：2006-08-03
申请人： James W. Adkisson , Jeffrey P. Gambino , Kirk D. Peterson , William R. Tonti
发明人： James W. Adkisson , Jeffrey P. Gambino , Kirk D. Peterson , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and a related method for fabricating the anti-fuse structure include a doped well within a semiconductor substrate. A first aperture and a second aperture that expose the doped well are located within a dielectric layer located over the semiconductor substrate and the doped well. A first conductor layer is located within the first aperture and a second conductor layer is located within the second aperture. At least a first anti-fuse material layer contacts the first conductor layer. The first conductor layer and the second conductor layer may comprise doped conductor materials that upon fusing of the anti-fuse structure provide an anti-fuse diode or an anti-fuse resistor.
摘要翻译：用于制造抗熔丝结构的反熔丝结构和相关方法包括半导体衬底内的掺杂阱。暴露掺杂阱的第一孔径和第二孔径位于位于半导体衬底和掺杂阱上方的电介质层内。第一导体层位于第一孔内，第二导体层位于第二孔内。至少第一反熔丝材料层接触第一导体层。第一导体层和第二导体层可以包括掺杂的导体材料，其在抗熔丝结构融合时提供抗熔丝二极管或抗熔丝电阻器。

25. 发明授权

US07141836B1 Pixel sensor having doped isolation structure sidewall 有权
标题翻译：具有掺杂隔离结构侧壁的像素传感器
公开(公告)号：US07141836B1
公开(公告)日：2006-11-28
申请号：US10908885
申请日：2005-05-31
申请人： James W. Adkisson , Mark D. Jaffe , Robert K. Leidy
发明人： James W. Adkisson , Mark D. Jaffe , Robert K. Leidy
IPC分类号： H01L27/148
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成隔离结构。隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿隔离结构中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

26. 发明授权

US06590259B2 Semiconductor device of an embedded DRAM on SOI substrate 有权
标题翻译： SOI衬底上嵌入式DRAM的半导体器件
公开(公告)号：US06590259B2
公开(公告)日：2003-07-08
申请号：US10000198
申请日：2001-11-02
申请人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
发明人： James W. Adkisson , Ramachandra Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman
IPC分类号： H01L2701
CPC分类号： H01L27/10864 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.
摘要翻译：提出了一种半导体器件，其涉及一种形成嵌入式DRAM和逻辑器件的方法，其中DRAM器件以块状形成，单晶半导体区域和逻辑器件形成在绝缘体上硅（“SOI”）区域中，其中掩埋的掺杂玻璃用作掩模以形成用于存储在本体区域中的深沟槽。还公开了所得到的结构。

27. 发明授权

US06448590B1 Multiple threshold voltage FET using multiple work-function gate materials 失效
标题翻译：多阈值电压FET采用多功能栅极材料
公开(公告)号：US06448590B1
公开(公告)日：2002-09-10
申请号：US09695199
申请日：2000-10-24
申请人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
发明人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
IPC分类号： H01L2710
CPC分类号： H01L29/4916 , H01L21/82345 , H01L29/4238 , H01L29/495 , H01L29/4966 , H01L29/66666 , H01L29/7827
摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
摘要翻译：通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。通过组合多个功能门极材料来开发多个阈值电压。栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。开发了用于多阈值电压设计的图案化线性阵列实施例。形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。栅极材料被布置成彼此靠近以适应小栅极长度设计。

28. 发明授权

US06300228B1 Multiple precipitation doping process 失效
标题翻译：多重沉淀掺杂工艺
公开(公告)号：US06300228B1
公开(公告)日：2001-10-09
申请号：US09386089
申请日：1999-08-30
申请人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
发明人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
IPC分类号： H01L2122
CPC分类号： H01L21/268 , H01L21/0455 , H01L21/2255
摘要： A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.
摘要翻译：用于掺杂半导体衬底（30）的多次沉淀掺杂工艺从在衬底（30）中形成无定形区域（32）开始。通过多次激光曝光，在覆盖非晶区域（32）的衬底（30）的主表面（31）的相应部分（34,37）上形成多个掺杂剂沉淀膜（52,53）。然后将衬底（30）退火。退火过程熔化非晶区域（32）并且允许沉淀在主表面（31）上的掺杂剂扩散到衬底（30）中。退火过程也使非晶区域（32）半导体材料结晶。基板（30）成为具有多个掺杂区域（54,57）的单晶半导体基板。掺杂区域（54,57）的深度基本上等于退火前非晶区域（32）的深度。

29. 发明授权

US06030541A Process for defining a pattern using an anti-reflective coating and structure therefor 失效
标题翻译：使用抗反射涂层定义图案的方法及其结构
公开(公告)号：US06030541A
公开(公告)日：2000-02-29
申请号：US100542
申请日：1998-06-19
申请人： James W. Adkisson , Michael Caterer , James T. Marsh , Hung Ng , James M. Oberschmidt , Jed H. Rankin
发明人： James W. Adkisson , Michael Caterer , James T. Marsh , Hung Ng , James M. Oberschmidt , Jed H. Rankin
IPC分类号： H01L21/027 , H01L21/28 , H01L21/3213 , H01L21/033
CPC分类号： H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： A pattern in a surface is defined by providing on the surface a hard mask material; depositing an anti-reflective coating on the hard mask material; applying a photoresist layer on the anti-reflective coating; patterning the photoresist layer, anti-reflective layer and hard mask material; and removing the remaining portions of the photoresist layer and anti-reflective layer; and then patterning the substrate using the hard mask as the mask. Also provided is a structure for defining a pattern in a surface which comprises a surface having a hard mask material thereon; an anti-reflective coating located on the hard mask material; and a photoresist located on the anti-reflective coating. Also provided is an etchant composition for removing the hard mask material which comprises an aqueous composition of HF and chlorine.
摘要翻译：通过在表面上提供硬掩模材料来限定表面中的图案; 在所述硬掩模材料上沉积抗反射涂层; 在抗反射涂层上施加光致抗蚀剂层; 图案化光致抗蚀剂层，抗反射层和硬掩模材料; 并除去光致抗蚀剂层和抗反射层的剩余部分; 然后使用硬掩模作为掩模来图案化衬底。还提供了一种用于在表面上限定图案的结构，其包括其上具有硬掩模材料的表面; 位于硬掩模材料上的抗反射涂层; 以及位于抗反射涂层上的光致抗蚀剂。还提供了用于除去硬掩模材料的蚀刻剂组合物，其包含HF和氯的水性组合物。

30. 发明授权

US09058455B2 Backside integration of RF filters for RF front end modules and design structure 有权
标题翻译：用于RF前端模块的RF滤波器的背面集成和设计结构
公开(公告)号：US09058455B2
公开(公告)日：2015-06-16
申请号：US13354705
申请日：2012-01-20
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC分类号： G06F17/50 , H01L21/768 , H01L23/48 , H03H9/64 , H01L23/00 , H01L27/06 , H01L49/02 , H01L23/66 , H01L25/16
CPC分类号： H01L41/293 , G06F17/5063 , G06F17/5068 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/24 , H01L25/16 , H01L27/0694 , H01L28/40 , H01L41/0815 , H01L41/25 , H01L2224/03009 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/12105 , H01L2224/14181 , H01L2224/16145 , H01L2224/24145 , H01L2225/06548 , H03H9/64
摘要： A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
摘要翻译：在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

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