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21. 发明授权

US5970311A Method and structure for optimizing the performance of a semiconductor device having dense transistors 失效
标题翻译：用于优化具有致密晶体管的半导体器件的性能的方法和结构
公开(公告)号：US5970311A
公开(公告)日：1999-10-19
申请号：US961980
申请日：1997-10-31
申请人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
发明人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/66 , H01L23/544 , H01L21/00 , G01R31/26
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/0002
摘要： A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate electrode formed at a design width and at a first line spacing similar to the line spacing of a dense transistor. One or more electrical properties the transistor of the first test structure is measured. A second test structure is formed on a second substrate portion. The second test structure includes a transistor having a gate electrode formed at the same design width as the transistor of the first test structure and at a second line spacing greater than the first line spacing. One or more electrical properties of the transistor of the second test structure are measured. Using the measured one or more electrical properties, one or more relationships are developed between the measured one or more electrical properties and the transistors at the first line spacing and the second line spacing.
摘要翻译：一种用于优化具有致密晶体管的半导体器件的性能的方法和结构。与本发明一致的方法包括在第一衬底部分上形成第一测试结构。第一测试结构包括晶体管，其晶体管具有以类似于致密晶体管的线间距的设计宽度和第一行间距形成的栅电极。测量第一测试结构的晶体管的一个或多个电特性。在第二基板部分上形成第二测试结构。第二测试结构包括晶体管，其晶体管具有与第一测试结构的晶体管相同的设计宽度并且在大于第一线间距的第二线间距处形成栅电极。测量第二测试结构的晶体管的一个或多个电特性。使用所测量的一个或多个电性能，在所测量的一个或多个电性能和在第一线间距和第二线间距处的晶体管之间形成一个或多个关系。

22. 发明授权

US07253484B2 Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
标题翻译：低功耗多通道全耗尽量子阱CMOSFET
公开(公告)号：US07253484B2
公开(公告)日：2007-08-07
申请号：US11445345
申请日：2006-06-02
申请人： James N. Pan , John G. Pellerin , Jon Cheek
发明人： James N. Pan , John G. Pellerin , Jon Cheek
IPC分类号： H01L27/088 , H01L29/78 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
摘要翻译：多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

23. 发明授权

US06833307B1 Method for manufacturing a semiconductor component having an early halo implant 失效
标题翻译：具有早期晕圈植入物的半导体部件的制造方法
公开(公告)号：US06833307B1
公开(公告)日：2004-12-21
申请号：US10284675
申请日：2002-10-30
申请人： Derick Wristers , Chad Weintraub , James F. Buller , Jon Cheek
发明人： Derick Wristers , Chad Weintraub , James F. Buller , Jon Cheek
IPC分类号： H01L21336
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823807 , H01L29/1045 , H01L29/665 , H01L29/6656 , H01L29/7835
摘要： An insulated gate field effect semiconductor component having a source-side halo region and a method for manufacturing the semiconductor component. A gate structure is formed on a semiconductor substrate. The source-side halo region is formed in the semiconductor substrate. After formation of the source-side halo region, spacers are formed adjacent opposing sides of the gate structure. A source extension region and a drain extension region are formed in the semiconductor substrate using an angled implant. The source extension region extends under the gate structure, whereas the drain extension may extend under the gate structure or be laterally spaced apart from the gate structure. A source region and a drain region are formed in the semiconductor substrate.
摘要翻译：具有源极侧卤素区域的绝缘栅场效应半导体元件和半导体元件的制造方法。栅极结构形成在半导体衬底上。在半导体衬底中形成源极侧晕区。在形成源极侧光晕区域之后，在栅极结构的相对侧附近形成间隔物。源极延伸区域和漏极延伸区域使用成角度的植入物形成在半导体衬底中。源极延伸区域在栅极结构下方延伸，而漏极延伸部可以在栅极结构下方延伸或者与栅极结构横向间隔开。在半导体衬底中形成源极区和漏极区。

24. 发明授权

US06674135B1 Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric 有权
标题翻译：在氮化物/氧化物电介质上具有升高的水银源/漏极区域和金属栅电极的半导体结构
公开(公告)号：US06674135B1
公开(公告)日：2004-01-06
申请号：US09199666
申请日：1998-11-25
申请人： Jon Cheek , Derick Wristers , Mark I. Gardner
发明人： Jon Cheek , Derick Wristers , Mark I. Gardner
IPC分类号： H01L2976
CPC分类号： H01L21/28202 , H01L21/28017 , H01L29/41766 , H01L29/41775 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/66628
摘要： A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.
摘要翻译：半导体结构及其制造方法。第一和第二栅极电介质层形成在氮化物间隔物之间的半导体衬底上，并且在栅极电介质层上形成金属栅电极。轻掺杂漏极区和源/漏区设置在衬底中并与电极和间隔物对准。硅化物接触层设置在源/漏区上的衬底上的外延层上。使用多晶硅取向结构对准金属栅电极，其可以在金属沉积之前进行高温处理。

25. 发明授权

US6104077A Semiconductor device having gate electrode with a sidewall air gap 失效
标题翻译：具有具有侧壁气隙的栅电极的半导体器件
公开(公告)号：US6104077A
公开(公告)日：2000-08-15
申请号：US60160
申请日：1998-04-14
申请人： Mark I. Gardner , Derick Wristers , Jon Cheek
发明人： Mark I. Gardner , Derick Wristers , Jon Cheek
IPC分类号： H01L21/266 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/28114 , H01L29/42376 , H01L29/4983 , H01L29/4991 , H01L29/665 , H01L29/6659
摘要： A semiconductor device having a gate electrode with a sidewall air gap is provided. In accordance with this embodiment, at least one gate electrode is formed over a substrate. A spacer is then formed adjacent an upper sidewall portion of the gate electrode such that an open area is left beneath the spacer. Next, a dielectric layer is formed over the spacer and the gate electrode, thereby leaving an air gap in the open area. In accordance with one aspect of the invention, both the gate electrode and the spacer adjacent the gate electrode are formed from polysilicon. This, for example, allows the formation of a wider contact area to the gate electrode.
摘要翻译：提供具有侧壁气隙的栅电极的半导体器件。根据本实施例，在衬底上形成至少一个栅电极。然后在栅电极的上侧壁部分附近形成间隔件，使得开口区域留在间隔件下方。接下来，在间隔物和栅电极之上形成介电层，从而在开放区域中留下空隙。根据本发明的一个方面，栅电极和与栅电极相邻的间隔物均由多晶硅形成。例如，这允许形成更宽的与栅电极的接触面积。

26. 发明授权

US5913116A Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer 失效
标题翻译：通过从侧壁间隔物扩散掺杂剂来制造半导体的有源区的方法
公开(公告)号：US5913116A
公开(公告)日：1999-06-15
申请号：US780455
申请日：1997-01-08
申请人： Mark I. Gardner , Jon Cheek
发明人： Mark I. Gardner , Jon Cheek
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864
摘要： In semiconductor device fabrication process, an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. In the fabrication process, a gate electrode having a sidewall adjacent an active region is formed on a substrate and a doped spacer layer having a dopant disposed therein is formed over the substrate and gate electrode. A portion of the spacer layer is then removed to form a spacer on the sidewall of the gate electrode. The dopant in the spacer is diffused into the substrate to form a lightly-doped region in the active region of the substrate. The lightly-doped region may form an LDD region of an LDD structure.
摘要翻译：在半导体器件制造工艺中，半导体器件的有源区通过从侧壁间隔物扩散出来形成。在制造工艺中，在衬底上形成具有邻近有源区的侧壁的栅电极，并且在衬底和栅电极上形成其中具有掺杂剂的掺杂间隔层。然后去除间隔层的一部分以在栅电极的侧壁上形成间隔物。间隔物中的掺杂剂扩散到衬底中以在衬底的有源区中形成轻掺杂区域。轻掺杂区域可以形成LDD结构的LDD区域。

27. 发明授权

US07235433B2 Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device 失效
标题翻译：具有不同晶体取向的硅层的绝缘体上半导体器件和形成绝缘体上硅半导体器件的方法
公开(公告)号：US07235433B2
公开(公告)日：2007-06-26
申请号：US10976780
申请日：2004-11-01
申请人： Andrew M. Waite , Jon Cheek
发明人： Andrew M. Waite , Jon Cheek
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78654
摘要： A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate with a silicon layer overlying the substrate and a first insulating layer interposed therebetween is provided. An opening is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer and the first insulating layer to expose a portion of the substrate layer. Selective epitaxial silicon is grown in the opening. A second insulating layer is formed in the silicon grown in the opening to provide an insulating layer between the grown silicon in the opening and the substrate.
摘要翻译：提供了包括具有第一晶体取向的衬底和覆盖在衬底上的绝缘层的半导体器件。在绝缘层上形成多个硅层。第一硅层包括具有第一晶体取向的硅，而第二硅层包含具有第二晶体取向的硅。此外，提供一种形成提供绝缘体上硅结构的半导体器件的方法，该半导体器件包括具有覆盖在衬底上的硅层的衬底和插入其间的第一绝缘层。通过去除硅层和第一绝缘层的一部分以露出衬底层的一部分，在绝缘体上硅结构的第一区域中形成开口。选择性外延硅在开口中生长。在开口中生长的硅中形成第二绝缘层，以在开口中的生长的硅和衬底之间提供绝缘层。

28. 发明申请

US20060091427A1 Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device 失效
标题翻译：具有不同晶体取向的硅层的绝缘体上半导体器件和形成绝缘体上硅半导体器件的方法
公开(公告)号：US20060091427A1
公开(公告)日：2006-05-04
申请号：US10976780
申请日：2004-11-01
申请人： Andrew Waite , Jon Cheek
发明人： Andrew Waite , Jon Cheek
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78654
摘要： A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate with a silicon layer overlying the substrate and a first insulating layer interposed therebetween is provided. An opening is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer and the first insulating layer to expose a portion of the substrate layer. Selective epitaxial silicon is grown in the opening. A second insulating layer is formed in the silicon grown in the opening to provide an insulating layer between the grown silicon in the opening and the substrate.
摘要翻译：提供了包括具有第一晶体取向的衬底和覆盖在衬底上的绝缘层的半导体器件。在绝缘层上形成多个硅层。第一硅层包括具有第一晶体取向的硅，而第二硅层包含具有第二晶体取向的硅。此外，提供一种形成提供绝缘体上硅结构的半导体器件的方法，该半导体器件包括具有覆盖在衬底上的硅层的衬底和插入其间的第一绝缘层。通过去除硅层和第一绝缘层的一部分以露出衬底层的一部分，在绝缘体上硅结构的第一区域中形成开口。选择性外延硅在开口中生长。在开口中生长的硅中形成第二绝缘层，以在开口中的生长的硅和衬底之间提供绝缘层。

29. 发明授权

US06300205B1 Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions 有权
标题翻译：制造具有自对准有源，轻掺杂漏极和卤区的半导体器件的方法
公开(公告)号：US06300205B1
公开(公告)日：2001-10-09
申请号：US09193262
申请日：1998-11-18
申请人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
发明人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.
摘要翻译：制造半导体器件的一种方法包括在衬底上形成栅电极并在栅电极的侧壁上形成间隔物。然后，使用第一掺杂剂材料，在衬底中形成有源区并与间隔物相邻，但与栅电极间隔开。使用不同于第一掺杂剂材料的导电类型的第二掺杂剂材料，在间隔物下方的衬底中形成晕圈区域并与有源区相邻。可以通过相对于衬底的表面以相对小于90°的角度将第二掺杂剂区域注入到衬底中来形成晕圈区域。然后去除间隔物的一部分，并且使用与第一掺杂剂材料相同的导电类型的第三掺杂剂材料，在邻近有源区和栅电极的衬底中形成轻掺杂区域，并且比晕区浅。

30. 发明授权

US6162694A Method of forming a metal gate electrode using replaced polysilicon structure 有权
标题翻译：使用取代的多晶硅结构形成金属栅电极的方法
公开(公告)号：US6162694A
公开(公告)日：2000-12-19
申请号：US199674
申请日：1998-11-25
申请人： Jon Cheek , Derick Wristers , Mark I Gardner
发明人： Jon Cheek , Derick Wristers , Mark I Gardner
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/66545
摘要： A metal gate electrode formed with high temperature activation of source/drain and LDD implants and a process for manufacture. A polysilicon alignment structure is formed on a silicon substrate. Source/drain regions are formed in alignment with the polysilicon alignment structure, and the alignment structure and the substrate are subjected to a first rapid thermal anneal. LDD implant regions are formed and the alignment structure and the substrate having the LDD regions are subjected to a second rapid thermal anneal. The polysilicon alignment structure is replaced with a metal gate electrode and gate dielectric.
摘要翻译：形成源/漏和LDD植入体的高温活化的金属栅电极和制造方法。在硅衬底上形成多晶硅取向结构。源/漏区形成为与多晶硅对准结构对准，并且对准结构和衬底经受第一快速热退火。形成LDD注入区，并且对准结构和具有LDD区的衬底进行第二次快速热退火。多晶硅取向结构被金属栅电极和栅极电介质代替。

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