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    • 22. 发明授权
    • Method of assembling a chip carrier
    • 组装芯片载体的方法
    • US4570337A
    • 1986-02-18
    • US599390
    • 1984-04-12
    • Sheldon H. Butt
    • Sheldon H. Butt
    • H01L23/14H01L23/495H05K1/03H05K1/05H05K3/42H05K3/34
    • H01L23/142H01L23/49537H05K1/053H01L2224/48227H01L2924/09701H01L2924/10253H05K1/0306H05K2201/0382H05K2203/068H05K3/42Y10S228/903Y10T29/49144Y10T428/12618
    • A chip carrier and a process of assembling a chip carrier are disclosed. The carrier used for mounting a chip comprises a copper or copper base alloy component having a thin refractory oxide layer on a surface thereof. The surface and the oxide layer have an indentation formed therein for receiving the chip. A metallic circuit pattern for electrical connection to the chip is bonded to the oxide layer and insulated from the copper or copper base alloy by the refractory oxide layer. A seal is provided for enclosing the chip to the indentation. Another embodiment of the invention includes a circuit board structure comprising a circuit board device having a first coefficient of thermal expansion. A chip carrier is provided having a second coefficient thermal expansion of substantially the same value as the first coefficient of thermal expansion. The chip carrier has electrical leads soldered to the circuit board whereby thermal cycling of the circuit board structure does not substantially stress the bond between the solder, leads and circuit board.
    • 公开了芯片载体和组装芯片载体的工艺。 用于安装芯片的载体包括在其表面上具有薄的难熔氧化物层的铜或铜基合金组分。 表面和氧化物层在其中形成有用于接收芯片的凹陷。 用于电连接到芯片的金属电路图案被结合到氧化物层并且通过难熔氧化物层与铜或铜基合金绝缘。 提供用于将芯片封装到压痕的密封件。 本发明的另一实施例包括一种包括具有第一热膨胀系数的电路板装置的电路板结构。 提供了具有与第一热膨胀系数基本相同的值的第二系数热膨胀的芯片载体。 芯片载体具有焊接到电路板的电引线,由此电路板结构的热循环基本上不会压迫焊料,引线和电路板之间的结合。