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21. 发明授权

US5930592A Asymmetrical n-channel transistor having LDD implant only in the drain region 失效
标题翻译：具有LDD注入的非对称n沟道晶体管仅在漏极区中
公开(公告)号：US5930592A
公开(公告)日：1999-07-27
申请号：US720733
申请日：1996-10-01
申请人： Daniel Kadosh , Brad T. Moore , Jon D. Cheek
发明人： Daniel Kadosh , Brad T. Moore , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/265
CPC分类号： H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/66659 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入只能在沟道的漏极侧，或在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

22. 发明授权

US5780340A Method of forming trench transistor and isolation trench 失效
标题翻译：形成沟槽晶体管和隔离沟槽的方法
公开(公告)号：US5780340A
公开(公告)日：1998-07-14
申请号：US739566
申请日：1996-10-30
申请人： Mark I. Gardner , Daniel Kadosh , Jon D. Cheek
发明人： Mark I. Gardner , Daniel Kadosh , Jon D. Cheek
IPC分类号： H01L21/336 , H01L21/76 , H01L29/78
CPC分类号： H01L29/66583 , H01L21/76 , H01L29/66613 , H01L29/66621 , H01L29/7834
摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.
摘要翻译：公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。沟槽形成在半导体衬底中。栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。基本上所有的栅电极都在晶体管沟槽内。衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。绝缘体填充绝缘体，并为IGFET提供器件隔离。有利地，使用单个蚀刻步骤同时形成沟槽。

23. 发明申请

US20100190354A1 INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于集成电路的中间层电介质
公开(公告)号：US20100190354A1
公开(公告)日：2010-07-29
申请号：US12752699
申请日：2010-04-01
申请人： James D. Burnett , Jon D. Cheek
发明人： James D. Burnett , Jon D. Cheek
IPC分类号： H01L21/31
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823807 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L27/1203 , H01L29/7843 , Y10S257/903
摘要： An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.
摘要翻译：具有逻辑和静态随机存取存储器（SRAM）阵列的集成电路通过针对SRAM阵列处理不同于逻辑的层间电介质（ILD）而提高了性能。 N沟道逻辑和SRAM晶体管具有非压缩应力的ILD，P沟道逻辑晶体管ILD具有压缩应力，P沟道SRAM晶体管至少具有比P沟道逻辑晶体管更小的压缩应力，即P沟道SRAM 晶体管可以是压缩的，但是比P沟道逻辑晶体管更小，可以被放宽，或者可以是拉伸的。 P沟道SRAM晶体管的集成电路具有比P沟道逻辑晶体管更低的迁移率是有益的。具有较低移动性的P沟道SRAM晶体管导致更好的写入性能; 在更低的电源电压下更好地写入时间或写入裕度。

24. 发明授权

US07422956B2 Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers 有权
公开(公告)号：US07422956B2
公开(公告)日：2008-09-09
申请号：US11006747
申请日：2004-12-08
申请人： Andrew Michael Waite , Jon D. Cheek
发明人： Andrew Michael Waite , Jon D. Cheek
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/76254 , H01L21/76267 , H01L21/76283 , H01L21/823412 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045
摘要： A semiconductor device comprising a substrate having a first crystal orientation is provided. A first insulating layer overlies the substrate and a plurality of silicon layers overlie the first insulating layer. A first silicon layer comprises silicon having a second crystal orientation and a crystal plane. A second silicon layer comprises silicon having the second crystal orientation and a crystal plane that is substantially orthogonal to the crystal plane of the first silicon layer. Because holes have higher mobility in the (110) plane than the (100) plane, while electrons have higher mobility in (100) plane than the (110) plane, semiconductor device performance can be enhanced by the selection of silicon layers with certain crystal plane orientations. In addition, a method of forming a semiconductor device is provided. A silicon-on-insulator structure comprising a first silicon substrate having a first crystal orientation with a first insulating layer formed thereon and a first silicon layer having a second crystal orientation and a crystal plane overlying the first insulating layer is bonded to a second silicon substrate. The second silicon substrate has the second crystal orientation and a crystal plane and a second insulating layer formed thereon. The second silicon substrate comprises a line of defects created by implanting hydrogen ion into the second silicon substrate. The crystal plane of the second silicon substrate is oriented substantially orthogonal to the crystal plane of the first silicon layer. The second silicon substrate is split and removed along the line of defects leaving behind the second insulating layer and a second silicon layer on the silicon-on-insulator structure. A plurality of devices with different crystal orientations can be subsequently formed on a single, planar silicon-on-insulator structure by selectively etching the silicon-on-insulator structure down to silicon layers of different crystal orientations, growing selective epitaxial silicon layers in the etched regions, and subsequently planarizing the silicon-on-insulator structure by chemical-mechanical polishing.

25. 发明授权

US07238990B2 Interlayer dielectric under stress for an integrated circuit 有权
标题翻译：集成电路应力下的层间电介质
公开(公告)号：US07238990B2
公开(公告)日：2007-07-03
申请号：US11100168
申请日：2005-04-06
申请人： James D. Burnett , Jon D. Cheek
发明人： James D. Burnett , Jon D. Cheek
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823807 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L27/1203 , H01L29/7843 , Y10S257/903
摘要： An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.
摘要翻译：具有逻辑和静态随机存取存储器（SRAM）阵列的集成电路通过针对SRAM阵列处理不同于逻辑的层间电介质（ILD）而提高了性能。 N沟道逻辑和SRAM晶体管具有非压缩应力的ILD，P沟道逻辑晶体管ILD具有压缩应力，P沟道SRAM晶体管至少具有比P沟道逻辑晶体管更小的压缩应力，即P沟道SRAM 晶体管可以是压缩的，但是比P沟道逻辑晶体管更小，可以被放宽，或者可以是拉伸的。 P沟道SRAM晶体管的集成电路具有比P沟道逻辑晶体管更低的迁移率是有益的。具有较低移动性的P沟道SRAM晶体管导致更好的写入性能; 在更低的电源电压下更好地写入时间或写入裕度。

26. 发明授权

US06580122B1 Transistor device having an enhanced width dimension and a method of making same 有权
标题翻译：具有增强的宽度尺寸的晶体管器件及其制造方法
公开(公告)号：US06580122B1
公开(公告)日：2003-06-17
申请号：US09812521
申请日：2001-03-20
申请人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
发明人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L2976
CPC分类号： G01N27/414
摘要： The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.
摘要翻译：本发明涉及一种具有增强的宽度尺寸的晶体管及其制造方法。在一个说明性实施例中，晶体管包括半导体衬底，形成在衬底中的凹陷隔离结构，隔离结构在其上限定凹陷，栅电极和位于衬底上方的栅极绝缘层，栅电极的一部分和栅极绝缘层延伸到凹陷隔离结构上方的凹部中，以及形成在衬底中的源极区域和漏极区域。在另一示例性实施例中，晶体管包括半导体衬底，限定具有上表面和暴露侧壁表面的有源区的凹陷隔离结构，位于上表面的一部分上方的栅绝缘层和栅电极，的有源区域的暴露的侧壁表面，以及形成在有源区域中的源极区域和漏极区域。

27. 发明授权

US06399493B1 Method of silicide formation by silicon pretreatment 有权
标题翻译：硅预处理硅化物形成方法
公开(公告)号：US06399493B1
公开(公告)日：2002-06-04
申请号：US09860141
申请日：2001-05-17
申请人： Robert Dawson , Jon D. Cheek , John G. Pellerin
发明人： Robert Dawson , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L29/665
摘要： Various methods of fabricating a silicide film and structures incorporating the same are provided. In one aspect, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide. The roughing of the silicon surface facilitates metal-silicide reactions.
摘要翻译：提供了制造硅化物膜的各种方法和结合其的结构。一方面，提供一种制造硅化物膜的方法，其包括在各向同性和各向异性蚀刻条件之间提供硅表面和蚀刻硅表面以在其上限定多个倾斜表面，从而增加硅表面的表面积。在多个倾斜表面上沉积硅化物形成材料，并加热硅表面以使硅化物形成材料与其反应并形成硅化物。硅表面的粗加工有助于金属硅化物反应。

28. 发明授权

US06358803B1 Method of fabricating a deep source/drain 有权
标题翻译：制造深源/漏极的方法
公开(公告)号：US06358803B1
公开(公告)日：2002-03-19
申请号：US09489369
申请日：2000-01-21
申请人： Mark Michael , Jon D. Cheek
发明人： Mark Michael , Jon D. Cheek
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/0847
摘要： Methods of fabricating source/drain regions and transistors incorporating the same are provided. In one aspect, a method of fabricating a source/drain region in a substrate is provided that includes forming a stack on the substrate with a gate electrode and an insulating layer positioned on the gate electrode that has etch selectivity to the gate electrode. A first doped region is formed in the substrate adjacent to the stack with a first horizontal junction. A second doped region is formed in the substrate that overlaps the first doped region and has a second horizontal junction positioned beneath the first horizontal junction. An implant of impurity ions into the substrate is performed to establish a third doped region that overlaps the second doped region and has a third horizontal junction positioned beneath the second horizontal junction. The insulating layer prevents impurity ions from substantially penetrating through the gate electrode. The substrate is heated to activate the first, the second and the third doped regions. A deep junctioned source/drain region is established without substantial impurity penetration into the gate electrode, resulting in improved junction capacitance.
摘要翻译：提供了制造源极/漏极区域的方法和结合其的晶体管。在一个方面，提供一种在衬底中制造源极/漏极区域的方法，其包括在衬底上形成具有栅极电极的绝缘层和位于栅电极上的对栅电极具有蚀刻选择性的绝缘层。第一掺杂区域形成在与第一水平连接点相邻的衬底的衬底中。第二掺杂区形成在衬底中，其与第一掺杂区重叠，并且具有位于第一水平结下方的第二水平结。执行将杂质离子注入到衬底中以建立与第二掺杂区重叠并具有位于第二水平结下方的第三水平结的第三掺杂区。绝缘层防止杂质离子基本上穿过栅电极。加热衬底以激活第一，第二和第三掺杂区域。建立了深接合的源极/漏极区，没有实质的杂质穿入栅电极，导致改善的结电容。

29. 发明授权

US06261885B1 Method for forming integrated circuit gate conductors from dual layers of polysilicon 有权
标题翻译：从双层多晶硅形成集成电路栅极导体的方法
公开(公告)号：US06261885B1
公开(公告)日：2001-07-17
申请号：US09497789
申请日：2000-02-03
申请人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
发明人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
IPC分类号： H01L218238
CPC分类号： H01L21/82345
摘要： A method for fabricating an integrated circuit is presented wherein a first polysilicon layer dielectrically spaced above a semiconductor substrate is provided. The semiconductor substrate contains a first active region and a second active region. A first dopant is selectively introduced into the portion of the first polysilicon layer above the second active region. A second polysilicon layer may then be formed upon the first polysilicon layer and above the first active region and the second active region. A second dopant may be selectively introduced into a portion of the second polysilicon layer above the first active region. The portion of the second polysilicon layer above the first active region and the portion of the first polysilicon layer above the first active region may be patterned to form a first gate structure within the first active region. The portion of the second polysilicon layer above the second active region and the portion of the first polysilicon layer above the second active region may be patterned to form a second gate structure within the second active region.
摘要翻译：提出了一种用于制造集成电路的方法，其中提供介于半导体衬底之上的第一多晶硅层。半导体衬底包含第一有源区和第二有源区。第一掺杂剂被选择性地引入第二有源区上方的第一多晶硅层的部分。然后可以在第一多晶硅层上并且在第一有源区和第二有源区上方形成第二多晶硅层。可以将第二掺杂剂选择性地引入第一有源区上方的第二多晶硅层的一部分。在第一有源区上方的第二多晶硅层的部分和第一有源区上方的第一多晶硅层的部分可以被图案化以在第一有源区内形成第一栅极结构。在第二有源区上方的第二多晶硅层的部分和第二有源区上方的第一多晶硅层的部分可以被图案化以在第二有源区内形成第二栅极结构。

30. 发明授权

US5981365A Stacked poly-oxide-poly gate for improved silicide formation 失效
标题翻译：用于改善硅化物形成的堆叠多晶氧化物多晶硅栅极
公开(公告)号：US5981365A
公开(公告)日：1999-11-09
申请号：US37530
申请日：1998-03-10
申请人： Jon D. Cheek , Derick J. Wristers , Mark I. Gardner
发明人： Jon D. Cheek , Derick J. Wristers , Mark I. Gardner
IPC分类号： H01L21/336 , H01L21/285
CPC分类号： H01L29/6659 , H01L29/41783 , H01L29/665 , H01L29/66545
摘要： A method of fabricating an integrated circuit transistor in a substrate is provided. A gate electrode stack is formed on the substrate. The stack has a first insulating layer, a first conductor layer on the first insulating layer, a second insulating layer on the first conductor layer, and a second conductor layer on the second insulating layer. First and second source/drain regions are formed in the substrate in spaced apart relation to define a channel region underlying the first insulating layer. First and second sidewall spacers are formed adjacent to the gate electrode stack. The second conductor layer and the second insulating layer are sacrificed and a silicide layer is formed on the first conductor layer. The void remaining after removal of the second conductor and insulating layers establishes a large separation between the silicide forming titanium layer and the first conductor layer. The result is a gate electrode stack that is resistant to lateral silicide formation due to silicon diffusion.
摘要翻译：提供了一种在衬底中制造集成电路晶体管的方法。在基板上形成栅电极堆叠。叠层具有第一绝缘层，第一绝缘层上的第一导体层，第一导体层上的第二绝缘层和第二绝缘层上的第二导体层。第一和第二源极/漏极区域以间隔开的关系形成在衬底中，以限定第一绝缘层下面的沟道区域。第一和第二侧壁间隔件邻近栅电极堆叠形成。牺牲第二导体层和第二绝缘层，在第一导体层上形成硅化物层。在去除第二导体和绝缘层之后残留的空隙在硅化物形成钛层和第一导体层之间形成大的间隔。结果是由于硅扩散而耐外部硅化物形成的栅电极堆叠。

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