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21. 发明申请

US20080108170A1 CMOS IMAGER WITH CU WIRING AND METHOD OF ELIMINATING HIGH REFLECTIVITY INTERFACES THEREFROM 失效
标题翻译：具有CU布线的CMOS成像器和消除其高反射性接口的方法
公开(公告)号：US20080108170A1
公开(公告)日：2008-05-08
申请号：US11959841
申请日：2007-12-19
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
IPC分类号： H01L21/04
CPC分类号： H01L27/14636 , H01L21/76819 , H01L21/76834 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14683
摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

22. 发明申请

US20070293025A1 PROTECT DIODES FOR HYBRID-ORIENTATION SUBSTRATE STRUCTURES 失效
标题翻译：用于混合基底结构的保护二极管
公开(公告)号：US20070293025A1
公开(公告)日：2007-12-20
申请号：US11849489
申请日：2007-09-04
申请人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
发明人： James Adkisson , Jeffrey Gambino , Alain Loiseau , Kirk Peterson
IPC分类号： H01L21/04
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.
摘要翻译：半导体结构制造方法。首先，提供半导体结构，其包括：（a）具有掺杂有第一掺杂极性且具有第一晶格取向的第一半导体材料的半导体块，以及（b）半导体块上的半导体区域，其中半导体区域是物理上的并且其中所述半导体区域包括掺杂有与所述第一掺杂极性相反的第二掺杂极性的第二半导体材料（i）和（ii）具有不同于所述第一晶格取向的第二晶格取向。接下来，分别在半导体块和半导体区域上形成第一和第二栅极叠层。然后，（i）第一和第二S / D区域同时形成在半导体块中的第一栅极堆叠的相对侧上，以及（ii）半导体块中的第一和第二放电预防半导体区域。

23. 发明申请

US20070187734A1 A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 失效
标题翻译：具有增强电容的CMOS成像器光电二极管
公开(公告)号：US20070187734A1
公开(公告)日：2007-08-16
申请号：US11276085
申请日：2006-02-14
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14689 , H01L31/035281
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.
摘要翻译：一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离，基材表面。在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于形成在基底表面处的掺杂层的下方。

24. 发明申请

US20070026617A1 Method of fabricating semiconductor side wall fin 有权
公开(公告)号：US20070026617A1
公开(公告)日：2007-02-01
申请号：US11495518
申请日：2006-07-31
申请人： James Adkisson , Paul Agnello , Arne Ballantine , Rama Divakaruni , Erin Jones , Edward Nowak , Jed Rankin
发明人： James Adkisson , Paul Agnello , Arne Ballantine , Rama Divakaruni , Erin Jones , Edward Nowak , Jed Rankin
IPC分类号： H01L21/336 , H01L27/12 , H01L21/20 , H01L21/44
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

25. 发明申请

US20060226456A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20060226456A1
公开(公告)日：2006-10-12
申请号：US10907570
申请日：2005-04-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

26. 发明申请

US20060110905A1 HIGH SURFACE AREA ALUMINUM BOND PAD FOR THROUGH-WAFER CONNECTIONS TO AN ELECTRONIC PACKAGE 有权
标题翻译：高表面积的铝合金焊盘，用于通过电缆连接到电子包装
公开(公告)号：US20060110905A1
公开(公告)日：2006-05-25
申请号：US10904677
申请日：2004-11-23
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Richard Rassel , Edmund Sprogis
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Richard Rassel , Edmund Sprogis
IPC分类号： H01L21/44 , H01L21/50
CPC分类号： H01L24/02 , H01L23/3114 , H01L23/481 , H01L2224/0401 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.
摘要翻译：用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

27. 发明申请

US20060102939A1 A CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 审中-公开
公开(公告)号：US20060102939A1
公开(公告)日：2006-05-18
申请号：US11276085
申请日：2006-02-14
申请人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
发明人： James Adkisson , John Ellis-Monaghan , Mark Jaffe , Dale Pearson , Dennis Rogers
IPC分类号： H01L31/062
摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

28. 发明申请

US20050030149A1 ELECTRICALLY TUNABLE ON-CHIP RESISTOR 失效
标题翻译：电气可控片上电阻
公开(公告)号：US20050030149A1
公开(公告)日：2005-02-10
申请号：US10604609
申请日：2003-08-04
申请人： James Adkisson , Anthony Stamper
发明人： James Adkisson , Anthony Stamper
IPC分类号： H01C10/00 , H01L27/08 , H01C7/10
CPC分类号： H01C10/00 , H01L27/0802
摘要： The present invention discloses a device having a resistor; a heater disposed proximate to the resistor and capable of raising the temperature of the resistor; a dielectric disposed between the heater and the resistor; and a tuner electrically coupled to the resistor, wherein the heater adjusts the resistance of the resistor in response to the tuner.
摘要翻译：本发明公开了一种具有电阻器的器件; 靠近电阻器设置并能够提高电阻器的温度的加热器; 设置在加热器和电阻器之间的电介质; 以及电耦合到所述电阻器的调谐器，其中所述加热器响应于所述调谐器调节所述电阻器的电阻。

29. 发明申请

US20050001216A1 Method of fabricating semiconductor side wall fin 有权
标题翻译：制造半导体侧壁翅片的方法
公开(公告)号：US20050001216A1
公开(公告)日：2005-01-06
申请号：US10867772
申请日：2004-06-16
申请人： James Adkisson , Paul Agnello , Arne Ballantine , Rama Divakaruni , Erin Jones , Edward Nowak , Jed Rankin
发明人： James Adkisson , Paul Agnello , Arne Ballantine , Rama Divakaruni , Erin Jones , Edward Nowak , Jed Rankin
IPC分类号： H01L29/161 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/423 , H01L29/786 , H01L29/76
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
摘要翻译：通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

30. 发明申请

US20080073742A1 STACKED IMAGE PACKAGE 有权
标题翻译：堆叠图像包
公开(公告)号：US20080073742A1
公开(公告)日：2008-03-27
申请号：US11943277
申请日：2007-11-20
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Stephen Luce , Richard Rassell , Edmund Sprogis
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Stephen Luce , Richard Rassell , Edmund Sprogis
IPC分类号： H01L31/00 , H01L21/98
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译：用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。互连装置提供例如与手机的空间限制相匹配的CSP。该布置还利用最小的线长度来降低噪声。将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

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