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21. 发明申请

US20070194397A1 PHOTO-SENSOR AND PIXEL ARRAY WITH BACKSIDE ILLUMINATION AND METHOD OF FORMING THE PHOTO-SENSOR 有权
标题翻译：具有背光照明的照相传感器和像素阵列以及形成照相传感器的方法
公开(公告)号：US20070194397A1
公开(公告)日：2007-08-23
申请号：US11276218
申请日：2006-02-17
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Alan Loiseau , Richard Rassel
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Alan Loiseau , Richard Rassel
IPC分类号： H01L31/0232 , H01L31/00
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/1463 , H01L27/1464 , H01L27/14689
摘要： An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.
摘要翻译：具有FET像素阵列的成像传感器和形成成像传感器的方法。每个像素是半导体岛，例如绝缘体上硅（SOI）晶片上的N型硅。 FET形成在一个光电二极管电极中，例如P阱阴极。滤色器可以附接到岛的相对表面。保护层（例如，玻璃或石英）或窗口在滤色器处固定到像素阵列。图像传感器可以从背面照亮，电池布线在电池单元上方。因此，通过保护层的光学信号被滤色器过滤并被相应的光电传感器选择性地感测。

22. 发明申请

US20060138480A1 A CMOS IMAGER WITH CU WIRING AND METHOD OF ELIMINATING HIGH REFLECTIVITY INTERFACES THEREFROM 有权
标题翻译：具有CU接线的CMOS成像器和消除其高反射性接口的方法
公开(公告)号：US20060138480A1
公开(公告)日：2006-06-29
申请号：US10905277
申请日：2004-12-23
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
IPC分类号： H01L31/113 , H01L31/0232 , H01L31/00
CPC分类号： H01L27/14636 , H01L21/76819 , H01L21/76834 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14683
摘要： An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
摘要翻译：一种图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光敏度的像素阵列。图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化。也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

23. 发明申请

US20060026472A1 Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects 失效
标题翻译：设计具有特定参数敏感度的扫描链来识别过程缺陷
公开(公告)号：US20060026472A1
公开(公告)日：2006-02-02
申请号：US10710642
申请日：2004-07-27
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

24. 发明申请

US20080108170A1 CMOS IMAGER WITH CU WIRING AND METHOD OF ELIMINATING HIGH REFLECTIVITY INTERFACES THEREFROM 失效
标题翻译：具有CU布线的CMOS成像器和消除其高反射性接口的方法
公开(公告)号：US20080108170A1
公开(公告)日：2008-05-08
申请号：US11959841
申请日：2007-12-19
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Richard Rassel , Anthony Stamper
IPC分类号： H01L21/04
CPC分类号： H01L27/14636 , H01L21/76819 , H01L21/76834 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14683
摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

25. 发明申请

US20060110905A1 HIGH SURFACE AREA ALUMINUM BOND PAD FOR THROUGH-WAFER CONNECTIONS TO AN ELECTRONIC PACKAGE 有权
标题翻译：高表面积的铝合金焊盘，用于通过电缆连接到电子包装
公开(公告)号：US20060110905A1
公开(公告)日：2006-05-25
申请号：US10904677
申请日：2004-11-23
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Richard Rassel , Edmund Sprogis
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Richard Rassel , Edmund Sprogis
IPC分类号： H01L21/44 , H01L21/50
CPC分类号： H01L24/02 , H01L23/3114 , H01L23/481 , H01L2224/0401 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.
摘要翻译：用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

26. 发明申请

US20080073742A1 STACKED IMAGE PACKAGE 有权
标题翻译：堆叠图像包
公开(公告)号：US20080073742A1
公开(公告)日：2008-03-27
申请号：US11943277
申请日：2007-11-20
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Stephen Luce , Richard Rassell , Edmund Sprogis
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Stephen Luce , Richard Rassell , Edmund Sprogis
IPC分类号： H01L31/00 , H01L21/98
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译：用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。互连装置提供例如与手机的空间限制相匹配的CSP。该布置还利用最小的线长度来降低噪声。将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

27. 发明申请

US20070087463A1 PIXEL SENSOR HAVING DOPED ISOLATION STRUCTURE SIDEWALL 有权
标题翻译：具有分离隔离结构的PIXEL传感器
公开(公告)号：US20070087463A1
公开(公告)日：2007-04-19
申请号：US11563531
申请日：2006-11-27
申请人： James Adkisson , Mark Jaffe , Robert Leidy
发明人： James Adkisson , Mark Jaffe , Robert Leidy
IPC分类号： H01L21/00
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffiusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a comer, or a comer portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离结构。沟槽隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散过程，由此在退火期间，存在于沿着沟槽中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。可替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其拐角部分来减小其尺寸来执行。

28. 发明申请

US20070114622A1 DAMASCENE COPPER WIRING OPTICAL IMAGE SENSOR 有权
标题翻译： DAMASCENE铜接线光学图像传感器
公开(公告)号：US20070114622A1
公开(公告)日：2007-05-24
申请号：US11623977
申请日：2007-01-17
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Anthony Stamper
IPC分类号： H01L29/82
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a inner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合具有改进的厚度均匀性的内部层间电介质叠层，以产生呈现增加的光敏度的像素阵列。在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。然后将蚀刻的开口用电介质材料重新填充。在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

29. 发明申请

US20060267013A1 PIXEL SENSOR HAVING DOPED ISOLATION STRUCTURE SIDEWALL 有权
标题翻译：具有分离隔离结构的PIXEL传感器
公开(公告)号：US20060267013A1
公开(公告)日：2006-11-30
申请号：US10908885
申请日：2005-05-31
申请人： James Adkisson , Mark Jaffe , Robert Leidy
发明人： James Adkisson , Mark Jaffe , Robert Leidy
IPC分类号： H01L29/04 , H01L29/768 , H01L27/148 , H01L29/76
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成隔离结构。隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿隔离结构中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

30. 发明申请

US20070259500A1 Structure Having Isolation Structure Including Deuterium Within A Substrate And Related Method 审中-公开
标题翻译：具有包含氘底物的隔离结构的结构及相关方法
公开(公告)号：US20070259500A1
公开(公告)日：2007-11-08
申请号：US11381861
申请日：2006-05-05
申请人： Kangguo Cheng , Oh-Jung Kwon , Deok-Kee Kim , James Adkisson
发明人： Kangguo Cheng , Oh-Jung Kwon , Deok-Kee Kim , James Adkisson
IPC分类号： H01L21/336 , H01L21/76 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/3003 , H01L21/76283 , H01L21/823481 , H01L29/66772 , H01L29/78 , H01L29/78654
摘要： Structures having an isolation structure including deuterium and a related method are disclosed. The deuterium is preferably substantially uniformly distributed, and has a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. One structure includes a substrate for a semiconductor device including an isolation structure within the substrate, the isolation structure including substantially uniformly distributed deuterium in a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. The substrate may include a semiconductor-on-insulator substrate. A method may include the steps of: providing an isolation structure in a substrate, the isolation structure including deuterium; and annealing to diffuse the deuterium into the substrate (prior to and/or after forming a gate dielectric). The structures and method provide a more efficient means for incorporating deuterium and reducing defects. In addition, the deuterium anneal can occur prior to gate dielectric formation during front-end-of-line processes, such that the anneal temperature can be high to improve deuterium incorporation with reduced anneal time.
摘要翻译：公开了具有包括氘的隔离结构的结构和相关方法。氘优选基本上均匀分布，并且具有大于在天然存在的氢气中发现的浓度（基于总氢原子含量）。一种结构包括用于半导体器件的衬底，该衬底包括衬底内的隔离结构，该隔离结构包括基本上均匀分布的氘，其浓度（基于总氢原子含量）大于在天然存在的氢中发现的浓度。衬底可以包括绝缘体上半导体衬底。一种方法可以包括以下步骤：在衬底中提供隔离结构，所述隔离结构包括氘; 和退火以将氘扩散到衬底中（在形成栅极电介质之前和/或之后）。结构和方法提供了一种更有效的方法来引入氘和减少缺陷。此外，氘退火可以在前端工艺过程中的栅极电介质形成之前发生，使得退火温度可以高以改善氘掺杂并减少退火时间。

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