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21. 发明申请

WO2007103854A2 HYBRID ORIENTATION SCHEME FOR STANDARD ORTHOGONAL CIRCUITS 审中-公开
标题翻译：标准正交电路的混合方向方案
公开(公告)号：WO2007103854A2
公开(公告)日：2007-09-13
申请号：PCT/US2007/063275
申请日：2007-03-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti
发明人： CHIDAMBARRAO, Dureseti
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/6659 , H01L29/7842
摘要： An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate (600), comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices (620) on the first areas and second type devices (630) on the second areas, wherein the first type devices (620) are parallel or perpendicular to the second type devices (630), and the first type devices (620) comprise a first current flow (621) and a second current flow (622) orthogonal to each other, wherein the carrier mobilities of the first (621) and second (622) current flows are equal to each other. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).
摘要翻译：本发明的实施例的集成电路包括混合取向衬底（600），其包括具有第一结晶取向的第一区域和具有第二结晶取向的第二区域。第一区域的第一晶体取向不平行或垂直于第二区域的第二晶体取向。集成电路还包括第一区域上的第一类型设备（620）和第二区域上的第二类型设备（630），其中第一类型设备（620）平行或垂直于第二类型设备（630），并且第一类型装置（620）包括彼此正交的第一电流（621）和第二电流（622），其中第一（621）和第二（622）电流的载流子迁移率彼此相等。具体地，第一类型器件包括p型场效应晶体管（PFET），第二类型器件包括n型场效应晶体管（NFET）。

22. 发明申请

WO2007045532A1 FIELD EFFECT TRANSISTORS (FETS) WITH INVERTED SOURCE/DRAIN METALLIC CONTACTS, AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有反相源/漏电金属接触的场效应晶体管（FET）及其制造方法
公开(公告)号：WO2007045532A1
公开(公告)日：2007-04-26
申请号：PCT/EP2006/066530
申请日：2006-09-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , BELYANSKY, Michael , CHIDAMBARRAO, Dureseti , CLEVENGER, Lawrence , KUMAR, Kaushik , RADENS, Carl
发明人： BELYANSKY, Michael , CHIDAMBARRAO, Dureseti , CLEVENGER, Lawrence , KUMAR, Kaushik , RADENS, Carl
IPC分类号： H01L21/768
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 µm2 to about 3.15 µm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 µm to about 5 µm.
摘要翻译：本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属触点，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。优选地，反相源极/漏极金属触点的下部具有约0.03μm2至约3.15μm2的横截面积，并且这样的反相源极/漏极金属触点与FET的栅电极间隔开一个距离范围为约0.001μm至约5μm。

23. 发明申请

WO2007038237A2 MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT 审中-公开
标题翻译：在单闸门上多个低K和高K门氧化物用于较低的电容和改进的驱动电流
公开(公告)号：WO2007038237A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/036916
申请日：2006-09-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , DOKUMACI, Omer , GLUSCHENKOV, Oleg , BELYANSKY, Michael
发明人： CHIDAMBARRAO, Dureseti , DOKUMACI, Omer , GLUSCHENKOV, Oleg , BELYANSKY, Michael
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/512 , H01L21/26586 , H01L21/31155 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, with the proviso that when the first gate oxide is high k, than the second gate oxide is low k, or when the first gate oxide is low k, than the second gate oxide is high k.
摘要翻译：本发明提供一种具有至少一个CMOS器件的半导体结构，其中米勒电容（即，重叠电容）被减小并且驱动电流得到改善。本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，条件是当第一栅极氧化物高于第二栅极氧化物为低k，或者当第一栅极氧化物为低k时，第二栅极氧化物为高k。

24. 发明申请

WO2005020318A1 SELF-ALIGNED DRAIN/CHANNEL JUNCTION IN VERTICAL PASS TRANSISTOR DRAM CELL DESIGN FOR DEVICE SCALING 审中-公开
标题翻译：用于设备放大的垂直通用晶体管DRAM单元设计中的自对准漏极/通道结
公开(公告)号：WO2005020318A1
公开(公告)日：2005-03-03
申请号：PCT/US2004/026058
申请日：2004-08-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , WANG, Geng , MCSTAY, Kevin , WEYBRIGHT, Mary, Elizabeth , LI, Yujun , CHIDAMBARRAO, Dureseti
发明人： WANG, Geng , MCSTAY, Kevin , WEYBRIGHT, Mary, Elizabeth , LI, Yujun , CHIDAMBARRAO, Dureseti
IPC分类号： H01L21/8234
CPC分类号： H01L27/10876 , H01L21/26586 , H01L27/10864 , H01L29/1041 , H01L29/66537 , H01L29/66666 , H01L29/7827 , H01L29/945
摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ + δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source region.
摘要翻译：提供了形成深沟槽垂直晶体管的方法。在掺杂半导体衬底中形成具有侧壁的深沟槽。半导体衬底在其表面中包括反向漏极区域和沿着侧壁的通道。漏极区域具有顶层和底层。反向掺杂的源极区域形成在与通道下方的侧壁并置的衬底中。栅极氧化层形成在与栅极导体并置的沟槽的侧壁上。执行将栅极导体凹入低于漏极区域的底部电平的步骤，然后相对于反向掺杂物的垂直角进行成角度的离子注入进入源极区域下方的沟道，并以一定角度进行成角度的离子注入相对于掺杂剂的垂直方向在源极区域下方的沟道中。

25. 发明申请

WO2010017010A1 IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD 审中-公开
标题翻译：具有VIABAR互连的IC和相关方法
公开(公告)号：WO2010017010A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/050919
申请日：2009-07-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , GRECO, Stephen, E. , LOW, Kia, S.
发明人： CHIDAMBARRAO, Dureseti , GRECO, Stephen, E. , LOW, Kia, S.
IPC分类号： H01L21/98
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

26. 发明申请

WO2008134105A1 SEMICONDUCTOR DEVICE STRESS MODELING METHODOLOGY 审中-公开
标题翻译：半导体器件应力建模方法
公开(公告)号：WO2008134105A1
公开(公告)日：2008-11-06
申请号：PCT/US2008/053149
申请日：2008-02-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , WILLIAMS, Richard, Q.
发明人： CHIDAMBARRAO, Dureseti , WILLIAMS, Richard, Q.
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5068 , G06F2217/16
摘要： A computational methodology that improves the accuracy of model parameters in a compact model uses methods and algorithms to self-consistently match independently developed base and stress models by re-fitting the stress model to the data set that generates the base model (310, 320). The re-fitting algorithm removes any discrepancy between the base model and the stress model as the stress model is applied to the data set obtained from a dimension-scaling macro. Stress offsets for dimension-scaling macro devices are calculated to fit the measured values of the model parameters for the same devices (340). The process of fitting the model parameters to the data set from the dimension-scaling macro calculates constant, linear, and quadratic coefficients for the model parameters, which are employed to increase the accuracy of the model parameters and of the compact model used in circuit simulations and optimization (360).
摘要翻译：提高紧凑模型中模型参数精度的计算方法使用方法和算法通过将应力模型重新拟合到生成基本模型的数据集（310,320）来自主一致地匹配独立开发的基础和应力模型，。随着应力模型应用于从尺寸缩放宏获取的数据集，重新拟合算法消除了基本模型和应力模型之间的任何差异。计算尺寸缩放宏设备的应力偏移量，以适应相同设备的模型参数的测量值（340）。将模型参数从维度缩放宏拟合到数据集的过程计算模型参数的常数，线性和二次系数，这些系数用于提高模型参数的精度和电路模拟中使用的紧凑模型和优化（360）。

27. 发明申请

WO2008014228A2 RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON 审中-公开
标题翻译：用于具有嵌入式硅碳的NMOSFET性能增强的提高的结构和超级散射技术
公开(公告)号：WO2008014228A2
公开(公告)日：2008-01-31
申请号：PCT/US2007/074169
申请日：2007-07-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHAKRAVARTI, Ashima, B. , CHIDAMBARRAO, Dureseti , HOLT, Judson, R. , LIU, Yaocheng , RIM, Kern
发明人： CHAKRAVARTI, Ashima, B. , CHIDAMBARRAO, Dureseti , HOLT, Judson, R. , LIU, Yaocheng , RIM, Kern
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si: C and polishing an etching the Si: C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si: C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

28. 发明申请

WO2007080048A1 SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVICES OF SAME CONDUCTIVE TYPE ON SAME SUBSTRATE 审中-公开
标题翻译：具有相同基板上的相同导电类型的低性能和高性能器件的半导体器件结构
公开(公告)号：WO2007080048A1
公开(公告)日：2007-07-19
申请号：PCT/EP2006/069984
申请日：2006-12-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , ARNOLD, John , CHIDAMBARRAO, Dureseti , LI, Ying , MALIK, Rajeev , NARASIMHA, Shreesh , PANDA, Siddhartha , TESSIER, Brian , WISE, Richard
发明人： ARNOLD, John , CHIDAMBARRAO, Dureseti , LI, Ying , MALIK, Rajeev , NARASIMHA, Shreesh , PANDA, Siddhartha , TESSIER, Brian , WISE, Richard
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/0922 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate (10); forming on the substrate a first gate (G1) with first spacers (SP), a second gate (G2) with second spacers (SP), respective source (S) and drain (D) regions of a same conductive type adjacent to the first gate and the second gate, an isolation region (STI) disposed intermediate of the first gate and the second gate, and silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers (RSPS) on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.
摘要翻译：一种制造半导体器件结构的方法，包括：提供衬底（10）; 在衬底上形成具有第一间隔物（SP）的第一栅极（G1），具有第二间隔物（SP）的第二栅极（G2），与第一间隔物（SP）相邻的相同导电类型的相应源极（S）和漏极（D）栅极和第二栅极，设置在第一栅极和第二栅极之间的隔离区域（STI），以及在第一栅极，第二栅极和相应的源极和漏极区域上的硅化物; 在第一间隔物上形成附加间隔物（RSPS）以产生中间结构，然后在整个中间结构上设置应力层。

29. 发明申请

WO2007054405A1 ROTATIONAL SHEAR STRESS FOR CHARGE CARRIER MOBILITY MODIFICATION 审中-公开
标题翻译：用于充电载波移动性修改的旋转剪切应力
公开(公告)号：WO2007054405A1
公开(公告)日：2007-05-18
申请号：PCT/EP2006/066992
申请日：2006-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHIDAMBARRAO, Dureseti
发明人： CHIDAMBARRAO, Dureseti
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L29/517 , H01L29/665 , H01L29/66575 , H01L29/7833 , H01L29/7846
摘要： A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region (11) mesa surrounded by an isolation trench. A first isolation region (12) having a first stress is located in the isolation trench. A second isolation region (16a, 16b) having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.
摘要翻译：半导体结构及其制造方法利用具有由隔离沟槽包围的有源区（11）台面的半导体衬底。具有第一应力的第一隔离区域（12）位于隔离沟槽中。具有不同于第一应力的第二应力的第二隔离区域（16a，16b）也位于隔离沟槽中。第一隔离区域和第二隔离区域的尺寸和尺寸被设置成对活性区域台面进行旋转剪切应力。

30. 发明申请

WO2006076535A1 ENHANCED PFET USING SHEAR STRESS 审中-公开
标题翻译：使用剪切应力的增强型PFET
公开(公告)号：WO2006076535A1
公开(公告)日：2006-07-20
申请号：PCT/US2006/001167
申请日：2006-01-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti
发明人： CHIDAMBARRAO, Dureseti
IPC分类号： H01L29/00
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823878 , H01L29/7842
摘要： A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of the trench isolation regions include stress materials such that the materials generate shear stresses in the channel region.
摘要翻译：半导体器件结构包括设置在衬底的一部分上的栅极结构，与该部分相邻设置的源极和漏极区域，以便在该部分中形成沟道区域，以及紧邻源极和漏极区域的沟槽隔离区域。沟槽隔离区域的至少一部分包括应力材料，使得材料在沟道区域中产生剪切应力。

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