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21. 发明授权

US08669641B2 Diffusion region routing for narrow scribe-line devices 有权
标题翻译：窄划线设备的扩散区域路由
公开(公告)号：US08669641B2
公开(公告)日：2014-03-11
申请号：US13164523
申请日：2011-06-20
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L21/78
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

22. 发明申请

US20100013059A1 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES 有权
标题翻译：用于NARROW SCRIBE-LINE设备的扩展区域路由
公开(公告)号：US20100013059A1
公开(公告)日：2010-01-21
申请号：US12173121
申请日：2008-07-15
申请人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
发明人： Ming-Chang Hsieh , Hung-Lin Chen , Hsiu-Mei Yu , Chin Kun Lan , Dong-Lung Lee
IPC分类号： H01L21/302 , H01L23/544
CPC分类号： H01L23/585 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
摘要翻译：本公开提供了一种制造集成电路（IC）装置的方法。该方法包括在半导体衬底中形成第一IC特征和第二IC特征，第一和第二IC特征彼此间隔开并由划线区分开; 在所述半导体衬底中至少部分地在所述划线区域内形成掺杂的布线特征并且被配置为连接所述第一和第二IC特征; 在所述半导体衬底上形成多层互连（MLI）结构和层间电介质（ILD），其中所述MLI被配置为在所述划线区域内不存在; 并且在刻划区域内蚀刻ILD和半导体衬底以形成划线沟槽。

23. 发明授权

US07364998B2 Method for forming high reliability bump structure 有权
标题翻译：形成高可靠性凸块结构的方法
公开(公告)号：US07364998B2
公开(公告)日：2008-04-29
申请号：US11185819
申请日：2005-07-21
申请人： Sung-Cheng Chiu , Hao-Yi Tsai , Hsiu-Mei Yu , Shih-Ming Chen , Shang-Yun Hou
发明人： Sung-Cheng Chiu , Hao-Yi Tsai , Hsiu-Mei Yu , Shih-Ming Chen , Shang-Yun Hou
IPC分类号： H01L21/44 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L2224/03912 , H01L2224/0401 , H01L2224/05001 , H01L2224/05017 , H01L2224/05027 , H01L2224/0554 , H01L2224/05556 , H01L2224/05559 , H01L2224/05572 , H01L2224/1147 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask. Thereafter, the electrically conductive material is reflowed to provide a bump on the semiconductor substrate.
摘要翻译：提供了在半导体衬底上形成凸块的方法，其上具有接触垫的衬底。在一个实施例中，该方法包括在衬底和接触垫上沉积钝化层。对钝化层进行图案化和蚀刻以在钝化层中形成暴露接触焊盘部分的多个开口。在蚀刻的钝化层上和其多个开口中沉积凸块下的冶金（UBM）层以接触接触焊盘。在UBM层上形成光致抗蚀剂层，然后对其进行图案化和蚀刻以形成基本上覆盖接触焊盘的至少一个开口。将导电材料沉积到形成在光致抗蚀剂层中的开口中，并覆盖UBM层并与接触垫对齐。去除剩余光致抗蚀剂层的一部分。使用导电材料作为掩模蚀刻UBM层。此后，导电材料回流以在半导体衬底上提供凸块。

24. 发明申请

US20060213804A1 Cavity structure for semiconductor structures 有权
标题翻译：半导体结构的腔结构
公开(公告)号：US20060213804A1
公开(公告)日：2006-09-28
申请号：US11166454
申请日：2005-06-24
申请人： Hsiu-Mei Yu , Gil Huang , Chien-Tung Yu , Owen Chen
发明人： Hsiu-Mei Yu , Gil Huang , Chien-Tung Yu , Owen Chen
IPC分类号： B65D85/00
CPC分类号： H01L27/14618 , H01L27/14632 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.
摘要翻译：提供了一种在半导体器件上提供空腔结构的方法。在封装图像传感器中特别有用的形成腔结构的方法包括在衬底上形成间隔层。间隔层可以由感光材料形成，光敏材料可以使用光刻技术进行图案化以在晶片上形成周围的模具的空腔壁。包装层，例如基本上透明的层，可以在固化之前直接放置在空腔壁上。在另一个实施例中，空腔壁被固化，将粘合剂施加到空腔壁的表面，并且将包装层放置在粘合剂上。此后，可以对晶片进行切割，并且可以将各个管芯封装使用。

25. 发明授权

US06624060B2 Method and apparatus for pretreating a substrate prior to electroplating 有权
标题翻译：在电镀前预处理基板的方法和装置
公开(公告)号：US06624060B2
公开(公告)日：2003-09-23
申请号：US10045782
申请日：2002-01-12
申请人： Kuo-Feng Chen , Hsiu-Mei Yu , Charles Tseng , Ta-Yang Lin
发明人： Kuo-Feng Chen , Hsiu-Mei Yu , Charles Tseng , Ta-Yang Lin
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , H01L24/10 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , Y10S134/902 , H01L2924/00
摘要： A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.
摘要翻译：一种方法，包括提供具有接触焊盘的衬底和覆盖接触焊盘的下凸块冶金的步骤，以及覆盖凸块下金属的光致抗蚀剂层，并且其中光致抗蚀剂层具有限定在其下的凸起到下凸块冶金并与接触垫对准。在第一种润湿溶液镀覆第一种子层之前，先在底部凸起冶金上预处理基材。此后，将第一种子层的电镀被镀在凸块下的金属上。

26. 发明授权

US06593220B1 Elastomer plating mask sealed wafer level package method 有权
标题翻译：弹性体电镀掩模密封晶圆级封装方法
公开(公告)号：US06593220B1
公开(公告)日：2003-07-15
申请号：US10038388
申请日：2002-01-03
申请人： Hsiu-Mei Yu , Ken-Shen Chou , Hsiu-Chieh Cheng , Shun-Liang Hsu
发明人： Hsiu-Mei Yu , Ken-Shen Chou , Hsiu-Chieh Cheng , Shun-Liang Hsu
IPC分类号： H01L2144
CPC分类号： H01L24/16 , H01L21/2885 , H01L23/3114 , H01L23/3171 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05572 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2224/05552 , H01L2924/00
摘要： A new method is provided for the creation of a solder mask for solder bump formation. A passivation layer is deposited on the semiconductor surface in the surface of which a contact pad has been provided, an opening is created in the layer of passivation that partially exposed the surface of the contact pad. A layer of UBM metal is deposited and patterned, limiting the layer of UBM to overlying and contacting the contact pad of the solder bump. A layer of elastomer is blanket deposited over the surface and patterned, creating an opening overlying the opening created in the layer of passivation, exposing the layer of UBM. The exposed surface of the layer of UBM is electroplated with a layer of solder, using the opening created in the layer of elastomer as the self-aligned electroplating opening. A step of reflow of the electroplated solder and the layer of elastomer completes the process of the invention, creating a solder bump surrounded by a layer of cured elastomer. Solder flow and elastomer curing are performed in the same step, and a special UBM design is used for the exposure of the UBM pad.
摘要翻译：提供了一种用于形成用于焊料凸点形成的焊接掩模的新方法。钝化层沉积在其表面上的半导体表面上，其中提供了接触焊盘，在钝化层中产生部分暴露接触焊盘表面的开口。沉积和图案化UBM金属层，限制UBM层覆盖并接触焊料凸块的接触焊盘。弹性体层被覆盖在表面上并被图案化，形成了覆盖在钝化层中形成的开口的开口，露出了UBM层。使用在弹性体层中形成的开口作为自对准电镀开口，用一层焊料电镀UBM层的暴露表面。电镀焊料和弹性体层的回流步骤完成了本发明的工艺，产生了由一层固化的弹性体包围的焊料凸块。焊接流程和弹性体固化在相同的步骤中进行，并且使用特殊的UBM设计来暴露UBM焊盘。

27. 发明授权

US5393697A Composite bump structure and methods of fabrication 失效
标题翻译：复合凸块结构及其制造方法
公开(公告)号：US5393697A
公开(公告)日：1995-02-28
申请号：US239424
申请日：1994-05-06
申请人： Shyh-Ming Chang , Yu-Chi Lee , Hsiu-Mei Yu , Li-Hui Yang , Jwo-huei Jou
发明人： Shyh-Ming Chang , Yu-Chi Lee , Hsiu-Mei Yu , Li-Hui Yang , Jwo-huei Jou
IPC分类号： H01L21/60 , H01L23/485 , H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/114 , H01L2224/116 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/1319 , H01L2224/13609 , H01L2224/13624 , H01L2224/13639 , H01L2224/13644 , H01L2224/13655 , H01L2224/13666 , H01L2924/0001 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01058 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14
摘要： A composite bump structure and methods of forming the composite bump structure. The composite bump structure comprises a polymer body of relatively low Young's Modulus compared to metals covered by a conductive metal coating formed at the input/output pads of an integrated circuit element or substrate. The composite bump is formed using material deposition, lithography, and etching techniques. A layer of soldering metal can be formed on the composite bumps if this is desired for subsequent processing.
摘要翻译：复合凸块结构和形成复合凸块结构的方法。与由在集成电路元件或衬底的输入/输出焊盘处形成的导电金属涂层覆盖的金属相比，复合凸块结构包括相对低的杨氏模量的聚合物体。使用材料沉积，光刻和蚀刻技术形成复合凸块。如果需要后续处理，可以在复合凸块上形成一层焊接金属。

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