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21. 发明授权

US5834851A SRAM having load transistor formed above driver transistor 失效
标题翻译：具有形成在驱动晶体管上方的负载晶体管的SRAM
公开(公告)号：US5834851A
公开(公告)日：1998-11-10
申请号：US460641
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。由两个字线限定的区域配置有两个驱动MISFET和源极线。源极线由与字线的导电层相同的导电层形成。互补数据线的各个数据线由与字线和源极线不同的导电层形成。字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线系统：采用双字线系统使用的子字线。

22. 发明授权

US5677887A Semiconductor memory device having a large storage capacity and a high speed operation 失效
标题翻译：具有大存储容量和高速操作的半导体存储器件
公开(公告)号：US5677887A
公开(公告)日：1997-10-14
申请号：US401693
申请日：1995-03-10
申请人： Koichiro Ishibashi , Katsuro Sasaki , Kunihiro Komiyaji , Toshiro Aoto , Sadayuki Morita
发明人： Koichiro Ishibashi , Katsuro Sasaki , Kunihiro Komiyaji , Toshiro Aoto , Sadayuki Morita
IPC分类号： G11C7/06 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/418 , G11C29/00 , G11C29/04 , G11C29/26 , G11C29/38 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： G11C29/70 , G11C11/418 , G11C29/26 , G11C29/38 , G11C29/78 , G11C7/06 , G11C8/14 , Y10S257/903 , Y10S257/904
摘要： A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically. In this case, the offset voltage of the sense amplifiers decreases significantly.
摘要翻译：具有增加的存储容量而不增加访问时间的半导体静态存储器件包括第一，第二和第三金属层。为了开始，转移MOSFET的字线由用于形成存储器件的转移MOSFET的栅电极的相同的多晶硅层形成。第一层的金属层用于本地字线，多晶硅字线和局部字线在其单元阵列的端部或内部连接。第二层的金属层用于位层，第三层的金属层用于主字线。因此，字线具有减小的时间常数，允许快速存储器访问。在存储器件中使用的读出放大器中的每一个都由具有分开设置在相邻位置的MOSFET构成。优选地，分割的MOSFET的栅电极对称地定位。在这种情况下，读出放大器的偏移电压显着降低。

23. 发明授权

US5126974A Sense amplifier for a memory device 失效
标题翻译：用于存储器件的感应放大器
公开(公告)号：US5126974A
公开(公告)日：1992-06-30
申请号：US465040
申请日：1990-01-16
申请人： Katsuro Sasaki , Katsuhiro Shimohigashi , Koichiro Ishibashi , Shoji Hanamura
发明人： Katsuro Sasaki , Katsuhiro Shimohigashi , Koichiro Ishibashi , Shoji Hanamura
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419 , G11C7/065
摘要： A MOS transistor sense amplifier employs cross coupled positive feedback for the load circuit of a differential amplifier with an equalizing switch at the amplifier output, and preferably also at the input. This basis amplifier circuit may be repeated in stages. When stages are employed, it is desirable that the first stage employs current mirror loading of the differential amplifier to reduce the data delay. Data delay is further reduced by providing strong amplification during the sense portion of the read cycle with a preamplifier, which preamplifier has its amplification reduced, preferably to unity by being turned off, when the sense portion of the cycle is finished, and most preferably when the input and output data lines are directly connected independently of the preamplifier, so that the preamplifier may be completely turned off to lower power consumption.
摘要翻译： MOS晶体管感测放大器采用交叉耦合的正反馈给差分放大器的负载电路，在放大器输出端具有均衡开关，优选也在输入端。该基本放大器电路可以分阶段地重复。当采用级时，期望第一级采用差分放大器的电流镜像负载来减少数据延迟。通过在读周期的感测部分期间通过在前置放大器上提供强放大来进一步降低数据延迟，当循环的感测部分完成时，前置放大器的放大减小，优选地被关闭，优选地，当输入和输出数据线独立于前置放大器直接连接，从而可以完全关闭前置放大器以降低功耗。

24. 发明授权

US5122857A Semiconductor memory device having first and second selecting lines for accessing memory cells 失效
标题翻译：具有访问存储器单元的第一和第二选择线的半导体存储器件
公开(公告)号：US5122857A
公开(公告)日：1992-06-16
申请号：US638768
申请日：1991-01-08
申请人： Shuji Ikeda , Katsuro Sasaki , Kouichi Nagasawa , Satoshi Meguro
发明人： Shuji Ikeda , Katsuro Sasaki , Kouichi Nagasawa , Satoshi Meguro
IPC分类号： H01L21/768 , G11C11/41 , H01L21/8244 , H01L23/522 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904 , Y10S257/906
摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM further has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

25. 发明授权

US5021944A Semiconductor memory having redundancy circuit for relieving defects 失效
标题翻译：具有用于消除缺陷的冗余电路的半导体存储器
公开(公告)号：US5021944A
公开(公告)日：1991-06-04
申请号：US376245
申请日：1989-07-06
申请人： Katsuro Sasaki , Katsuhiro Shimohigashi , Shoji Hanamura
发明人： Katsuro Sasaki , Katsuhiro Shimohigashi , Shoji Hanamura
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
CPC分类号： G11C29/846
摘要： A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare memory array. A first word from the first memory array is selected concurrently with a first substitute word from the first spare memory. An address signal is decoded and then compared with data representative of a defective word. In the event it is determined, as a result of this comparison, that the first word is defective, the first substitute word is then communicated to a common data bus. Alternatively, the first word is communicated to the common data bus.
摘要翻译：用替代存储器元件快速掩蔽有缺陷的存储器元件的方法和装置包括第一和第二存储器块。第一存储器块包括第一存储器阵列和第二备用存储器阵列。第二存储器块包括第二存储器阵列和第一备用存储器阵列。与来自第一备用存储器的第一替代字同时选择来自第一存储器阵列的第一个字。地址信号被解码，然后与表示有缺陷的字的数据进行比较。在确定的情况下，作为该比较的结果，第一个字是有缺陷的，然后第一个替代字被传送到公共数据总线。或者，第一个字被传送到公共数据总线。

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