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21. 发明授权

US08163556B2 Method of cell culture observation, carbon substrate for cell culture observation, and method for manufacture thereof 有权
标题翻译：细胞培养观察方法，细胞培养观察用碳底物及其制造方法
公开(公告)号：US08163556B2
公开(公告)日：2012-04-24
申请号：US11276263
申请日：2006-02-21
申请人： Yoshihisa Suda , Kunitaka Yamada , Hiroko Kaneko , Kaoru Katoh , Harumasa Okamoto
发明人： Yoshihisa Suda , Kunitaka Yamada , Hiroko Kaneko , Kaoru Katoh , Harumasa Okamoto
IPC分类号： C01B31/00 , B32B5/02 , B32B27/04 , G01N21/00 , C12N5/00
CPC分类号： C12N5/0068 , B82Y30/00 , C12N2533/10 , G01N21/6458 , Y10T436/11
摘要： The invention provides a substrate suitable for cell culture observation and a method of observation using the same. Crystalline carbon such as a graphite powder is mixed into a thermosetting resin such as a furan resin, and the mixture is molded in the shape of a sheet and carbonized to produce a carbon substrate; then, a cell is made to adhere to the carbon substrate, and the cell is caused to proliferate on the carbon substrate and observed using a microscope.
摘要翻译：本发明提供适用于细胞培养观察的底物和使用其的观察方法。将诸如石墨粉末的结晶碳混合到诸如呋喃树脂的热固性树脂中，并将该混合物模制成片状并碳化以产生碳基底; 然后，使电池附着在碳基板上，并使电池在碳基板上增殖并用显微镜观察。

22. 发明授权

US06838175B2 Carbon microrod and method of producing the same 失效
标题翻译：碳微球及其制造方法
公开(公告)号：US06838175B2
公开(公告)日：2005-01-04
申请号：US10058301
申请日：2002-01-30
申请人： Kaoru Katoh , Masahiro Yamada , Hiroko Kaneko , Yoshihisa Suda
发明人： Kaoru Katoh , Masahiro Yamada , Hiroko Kaneko , Yoshihisa Suda
IPC分类号： B81B7/02 , B01J20/20 , C01B31/02 , C04B35/52 , C04B35/524 , C04B35/634 , D01F9/12 , B32B9/00
CPC分类号： C04B35/524 , B01J20/20 , C04B35/522 , C04B35/632 , C04B35/634 , C04B2235/425 , C04B2235/48 , C04B2235/6021 , C04B2235/94 , C04B2235/96 , D01F9/12 , Y10T428/298 , Y10T428/30
摘要： A carbon microrod that holds a fine object by chemically adsorbing the object on the surface to make a dynamic measurement possible. An organic substance that leaves, after firing, glassy carbon that hardly becomes graphite, such as a chlorinated vinyl chloride resin, is mixed with a fine graphite powder having an average particle size of 1 μm, and the mixture is extrusion molded with a die having a diameter of 50 μm; the molded article is fired to give a carbon microrod comprising glassy carbon and crystalline carbon.
摘要翻译：通过化学吸附表面上的物体来保持细微物体以进行动态测量的碳微轨道。在烧成之后，将几乎不成为石墨的玻璃碳（例如氯化氯乙烯树脂）与平均粒径为1μm的细石墨粉末混合，并将该混合物用具有直径50um; 将模塑制品烧制，得到包含玻璃碳和结晶碳的碳微球。

23. 发明授权

US5734188A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
公开(公告)号：US5734188A
公开(公告)日：1998-03-31
申请号：US674185
申请日：1996-07-01
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L27/105 , H01L29/76 , H01L29/94 , H01L31/062 , H01L3/119
CPC分类号： H01L27/105
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

24. 发明授权

US5153685A Semiconductor integrated circuit device having switching MISFET and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring 失效
标题翻译：具有开关MISFET和电容器元件的半导体集成电路器件及其制造方法，包括其布线及其制造方法
公开(公告)号：US5153685A
公开(公告)日：1992-10-06
申请号：US246514
申请日：1988-09-19
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided. In the sixth aspect, an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; in the seventh aspect, a refractory metal, or a refractory metal silicide QSI.sub.x, where Q is a refractory metal and 0
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。在第二方面，Y选择信号线与电容器元件的下电极层重叠。在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。在第六和第七方面中，提供了布线。在第六方面中，在相同的真空溅射室中通过溅射形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 在第七方面中，将含有添加元素（例如Cu）的铝配线用作难熔金属或难熔金属硅化物QSIx（其中Q为难熔金属且0

25. 发明授权

US07436294B2 Method and apparatus for disaster prevention 有权
标题翻译：防灾方法和装置
公开(公告)号：US07436294B2
公开(公告)日：2008-10-14
申请号：US11193454
申请日：2005-08-01
申请人： Susumu Saga , Yasuyuki Kawaida , Hiroko Kaneko
发明人： Susumu Saga , Yasuyuki Kawaida , Hiroko Kaneko
IPC分类号： G08B29/00
CPC分类号： G08B7/066 , G08B27/001
摘要： An apparatus, which is for disaster prevention installed in a facility, includes a radio-frequency identification tag that stores at least one of a first data and a second data. The first data is related to the disaster prevention, and is transmitted by wireless communication. The second data is related to the disaster prevention, and is received by wireless communication.
摘要翻译：一种用于安装在设施中的防灾装置，包括存储第一数据和第二数据中的至少一个的射频识别标签。第一个数据与防灾相关，并通过无线通信传输。第二个数据与防灾相关，并通过无线通信接收。

26. 发明授权

US06281071B1 Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring therefor and method of producing such wiring 失效
标题翻译：具有开关MISFET和包括其布线的电容器元件的半导体集成电路器件的制造方法以及制造这种布线的方法
公开(公告)号：US06281071B1
公开(公告)日：2001-08-28
申请号：US09317999
申请日：1999-05-25
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。在第二方面，Y选择信号线与电容器元件的下电极层重叠。在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。在第六和第七方面中，提供了布线。

27. 发明授权

US5917211A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法及其制造装置
公开(公告)号：US5917211A
公开(公告)日：1999-06-29
申请号：US979543
申请日：1997-11-25
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/08 , H01L29/76 , H01L29/94
CPC分类号： H01L27/105 , H01L21/823425
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
摘要翻译：一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

28. 发明授权

US5753550A Semiconductor integrated circuit device having switching MISFET and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring 失效
标题翻译：具有开关MISFET和电容器元件的半导体集成电路器件及其制造方法，包括其布线及其制造方法
公开(公告)号：US5753550A
公开(公告)日：1998-05-19
申请号：US620867
申请日：1996-03-25
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。在第一方面中，电容器元件所连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成在高压下通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

29. 发明授权

US4701349A Semiconductor integrated circuit device and method of producing the same 失效
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US4701349A
公开(公告)日：1987-10-20
申请号：US806342
申请日：1985-12-09
申请人： Mitsumasa Koyanagi , Hiroko Kaneko
发明人： Mitsumasa Koyanagi , Hiroko Kaneko
IPC分类号： H01L29/78 , H01L21/285 , H01L21/321 , H01L21/3213 , H01L29/45 , H01L29/49
CPC分类号： H01L21/32134 , H01L21/28518 , H01L21/3211 , H01L29/456 , H01L29/4933
摘要： A silicide layer of a refractory metal for reducing resistance and a nitride layer for preventing diffusion of aluminum are formed on the source and drain regions of an MISFET. The silicide layer is formed in self-alignment with the source and drain regions by two annealings effected at a low temperature and at a high temperature, respectively, and has a low resistance. The nitride layer is formed by directly nitriding the silicide layer.
摘要翻译：在MISFET的源极和漏极区域上形成用于降低电阻的难熔金属的硅化物层和用于防止铝的扩散的氮化物层。硅化物层通过在低温和高温下分别进行两次退火而与源极和漏极区域自对准形成，并具有低电阻。通过直接氮化硅化物层形成氮化物层。

30. 发明授权

US4521081A Electrochromic display device 失效
标题翻译：电致变色显示装置
公开(公告)号：US4521081A
公开(公告)日：1985-06-04
申请号：US361874
申请日：1982-03-25
申请人： Kiyoshi Miyake , Hiroko Kaneko
发明人： Kiyoshi Miyake , Hiroko Kaneko
IPC分类号： C09K9/00 , G02F1/15 , G02F1/17
CPC分类号： G02F1/1523 , C09K9/00
摘要： A process for forming an electrochromic film to be used in an electrochromic device is provided. The process includes a step of introducing a mixture of oxygen gas and inert gas at a predetermined mixing ratio into a reactor in which is provided an electrode having thereon a sheet of tungsten as a target and a counter-electrode holding thereon a substrate under a predetermined total pressure condition and a step of applying a predetermined voltage between said electrodes while maintaining the substrate at a predetermined temperature. The present process allows to provide a WO.sub.3 -sputtered film on the substrate. The present invention also provides an electrochromic display device in which the electrochromic film is operated under control not to reach the color saturation condition, thereby preventing the occurrence of separation of the film and thus ensuring a long-term servicelife.
摘要翻译：提供一种用于形成用于电致变色装置中的电致变色膜的方法。该方法包括以预定的混合比将氧气和惰性气体的混合物引入反应器中的步骤，在该反应器中设置有在其上具有钨片作为靶的电极和在其上保持预定的基板的对置电极总压力条件和在所述电极之间施加预定电压同时将衬底保持在预定温度的步骤。本方法允许在衬底上提供WO3溅射膜。本发明还提供一种电致变色显示装置，其中电致变色膜在控制下操作不达到色饱和状态，从而防止膜分离的发生，从而确保长期的服务。

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