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    • 22. 发明授权
    • Terminal
    • 终奌站
    • US06353863B1
    • 2002-03-05
    • US09051286
    • 1998-12-01
    • Tetsuya NakagawaYuji HatanoYasuhiro SagesakaToru BajiKoki Noguchi
    • Tetsuya NakagawaYuji HatanoYasuhiro SagesakaToru BajiKoki Noguchi
    • G06F300
    • G06F9/3885G06F1/3203G06F15/7807
    • A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
    • 低成本,低功耗和小尺寸是移动通信终端的三个非常重要的因素。 使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题,需要两个外部存储器系统。 此外,DSP和CPU的数据输入和输出需要两个外设单元。 因此,DSP和CPU之间会发生无关的通信开销。 本发明通过DSP / CPU集成芯片实现移动通信终端系统,其包括集成为单总线主机的DSP / CPU核心(500),集成外部总线接口(606)和集成外围电路接口。 因此,DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。
    • 24. 发明授权
    • Information processing apparatus
    • 信息处理装置
    • US4809206A
    • 1989-02-28
    • US87346
    • 1987-08-20
    • Atsushi KiuchiKenji KanekoJun IshidaTetsuya NakagawaYoshimune HagiwaraHirotada Ueda
    • Atsushi KiuchiKenji KanekoJun IshidaTetsuya NakagawaYoshimune HagiwaraHirotada Ueda
    • G06F9/34G06F7/544G06F12/02G06F17/10H03H17/02G06F7/38
    • G06F7/5443
    • This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.Contrivances are made in order to set the number of a plurality of data that are stored in the data memory for repetition of use, to an arbitrary value.
    • 本发明涉及诸如数字信号处理器的信息处理设备,并且特别适用于数字滤波器。 从初始值数据到与数字滤波器的滤波系数相关的最终值数据的多个数据被存储在数据存储器中,并且通过地址运算单元的增量操作被依次读出。 数据运算单元依次执行依次读出的多个数据和顺序输入的数字输入信号的乘积和/或和运算,进行数字信号处理。 该信息处理装置特别地具有如下装置:当访问地址从初始值开始时,由于增量操作而超过最终值并达到返回地址,自动将访问地址返回到初始值。 因此,可以重复使用存储在数据存储器中的多个数据。 为了将存储在用于重复使用的数据存储器中的多个数据的数量设置为任意值,进行了操作。