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21. 发明申请

US20130214364A1 REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER 审中-公开
标题翻译：替代铝电极与钨合金金属层
公开(公告)号：US20130214364A1
公开(公告)日：2013-08-22
申请号：US13398314
申请日：2012-02-16
申请人： Hemanth Jagannathan , Vamsi K. Paruchuri
发明人： Hemanth Jagannathan , Vamsi K. Paruchuri
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823821 , H01L21/823842 , H01L21/84 , H01L27/0924 , H01L27/1203 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate.
摘要翻译：钽合金层用作场效晶体管的功函数金属。钽合金层可以选自TaC，TaAl和TaAlC。当与金属氮化物层组合使用时，钽合金层和金属氮化物层提供两个功函数值，其差值为300mV〜500mV，从而使多个场效应晶体管具有不同的阈值电压。钽合金层可以与第一栅极中的第一栅极电介质接触，并且金属氮化物层可以与具有与第一栅极电介质相同的组成和厚度并位于第二栅极中的第二栅极电介质接触。

22. 发明申请

US20130221441A1 REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS 有权
标题翻译：具有多层导电金属氮化物层的更换栅极电极
公开(公告)号：US20130221441A1
公开(公告)日：2013-08-29
申请号：US13406784
申请日：2012-02-28
申请人： Hemanth Jagannathan , Vamsi K. Paruchuri
发明人： Hemanth Jagannathan , Vamsi K. Paruchuri
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/28229 , H01L21/823842 , H01L21/823871 , H01L21/845 , H01L23/485 , H01L27/092 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.
摘要翻译：可以通过在替代栅极方案中提供具有不同厚度的导电金属氮化物层来提供具有不同功函数的栅电极。在去除一次性栅极结构和形成栅极电介质层时，至少一个增量厚度的导电金属氮化物层被添加到一些栅极空腔内，而不被添加到一些其它栅极腔中。随后添加最小厚度的导电金属氮化物层作为连续层。如此形成的导电金属氮化物层在不同的栅腔上具有不同的厚度。沉积栅极填充导电材料层，并执行平面化以提供具有不同导电金属氮化物层厚度的多个栅电极。导电金属氮化物层的不同厚度可以提供具有约400mV范围的不同功函数。

23. 发明授权

US08232179B2 Method to improve wet etch budget in FEOL integration 有权
标题翻译：在FEOL集成中改善湿法蚀刻预算的方法
公开(公告)号：US08232179B2
公开(公告)日：2012-07-31
申请号：US12571483
申请日：2009-10-01
申请人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

24. 发明申请

US20110303981A1 Scheme to Enable Robust Integration of Band Edge Devices and Alternatives Channels 审中-公开
标题翻译：实现带边缘设备和替代通道鲁棒集成的方案
公开(公告)号：US20110303981A1
公开(公告)日：2011-12-15
申请号：US12797431
申请日：2010-06-09
申请人： Lisa F. Edge , Hemanth Jagannathan , Bala Subramanian Haran
发明人： Lisa F. Edge , Hemanth Jagannathan , Bala Subramanian Haran
IPC分类号： H01L27/12 , H01L21/20
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L21/845
摘要： A method of forming a semiconductor device includes forming a buried oxide (BOX) layer on a semiconductor substrate, forming a silicon-on-insulator (SOI) layer on the BOX layer, depositing a hard mask including one of silicon, a nitride, and a metal oxide on the SOI layer, removing the hard mask from a first region of the semiconductor device, performing a cleaning process on the semiconductor device, wherein the hard mask is not removed from a second region of the semiconductor device by the cleaning process, epitaxially growing a semiconductor material in the first region of the semiconductor device, and removing the hard mask from the second region of the semiconductor device.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成掩埋氧化物（BOX）层，在BOX层上形成绝缘体上硅（SOI）层，沉积包括硅，氮化物和所述SOI层上的金属氧化物，从所述半导体器件的第一区域去除所述硬掩模，对所述半导体器件执行清洁处理，其中所述硬掩模不通过所述清洁处理从所述半导体器件的第二区域移除，在半导体器件的第一区域中外延生长半导体材料，以及从半导体器件的第二区域去除硬掩模。

25. 发明申请

US20110081765A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 有权
标题翻译：提高生产费用总额的方法
公开(公告)号：US20110081765A1
公开(公告)日：2011-04-07
申请号：US12571483
申请日：2009-10-01
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

26. 发明授权

US09093558B2 Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate 有权
标题翻译：使用全金属栅极集成多个阈值电压器件用于互补金属氧化物半导体
公开(公告)号：US09093558B2
公开(公告)日：2015-07-28
申请号：US13594772
申请日：2012-08-24
申请人： Lisa F. Edge , Hemanth Jagannathan , Balasubramanian S. Haran
发明人： Lisa F. Edge , Hemanth Jagannathan , Balasubramanian S. Haran
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/823835 , H01L21/823842 , H01L27/088 , H01L29/45 , H01L29/4966 , H01L29/517
摘要： A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.
摘要翻译：提供了基板，其上形成有与第一区域互补的第一区域和第二区域。在衬底上沉积栅极电介质，并且在栅极电介质上沉积第一全金属栅极堆叠。在第一区域上去除第一个全金属栅极叠层，以产生结果。在所得到的结构上，在第一区域上沉积与栅极电介质接触的第二全金属栅极堆叠。第一和第二全金属栅极堆叠被封装。

27. 发明授权

US08679941B2 Method to improve wet etch budget in FEOL integration 失效
标题翻译：在FEOL集成中改善湿法蚀刻预算的方法
公开(公告)号：US08679941B2
公开(公告)日：2014-03-25
申请号：US13422138
申请日：2012-03-16
申请人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E Cummings , Lisa F Edge , Balasubramanian S. Haran , David V Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

28. 发明申请

US20140054717A1 INTEGRATION OF MULTIPLE THRESHOLD VOLTAGE DEVICES FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR USING FULL METAL GATE 有权
标题翻译：使用全金属栅组合多个金属氧化物半导体的多个阈值电压装置
公开(公告)号：US20140054717A1
公开(公告)日：2014-02-27
申请号：US13594772
申请日：2012-08-24
申请人： Lisa F. Edge , Hemanth Jagannathan , Balasubramanian S. Haran
发明人： Lisa F. Edge , Hemanth Jagannathan , Balasubramanian S. Haran
IPC分类号： H01L21/283 , H01L27/092
CPC分类号： H01L27/0922 , H01L21/28088 , H01L21/823835 , H01L21/823842 , H01L27/088 , H01L29/45 , H01L29/4966 , H01L29/517
摘要： A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.
摘要翻译：提供了基板，其上形成有与第一区域互补的第一区域和第二区域。在衬底上沉积栅极电介质，并且在栅极电介质上沉积第一全金属栅极堆叠。在第一区域上去除第一个全金属栅极叠层，以产生结果。在所得到的结构上，在第一区域上沉积与栅极电介质接触的第二全金属栅极堆叠。第一和第二全金属栅极堆叠被封装。

29. 发明申请

US20120178236A1 METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 失效
标题翻译：提高生产费用总额的方法
公开(公告)号：US20120178236A1
公开(公告)日：2012-07-12
申请号：US13422138
申请日：2012-03-16
申请人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Lisa F. Edge , Balasubramanian S. Haran , David V. Horak , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
摘要翻译：提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

30. 发明授权

US09006094B2 Stratified gate dielectric stack for gate dielectric leakage reduction 有权
标题翻译：用于栅介质泄漏减少的分层栅极电介质叠层
公开(公告)号：US09006094B2
公开(公告)日：2015-04-14
申请号：US13449647
申请日：2012-04-18
申请人： Hemanth Jagannathan , Paul C. Jamison
发明人： Hemanth Jagannathan , Paul C. Jamison
IPC分类号： H01L21/20 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L21/28
CPC分类号： H01L21/283 , H01L21/28158 , H01L21/28202 , H01L21/28211 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L29/7833 , H01L29/785
摘要： A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.
摘要翻译：分层栅极电介质堆叠包括第一高介电常数（high-k）栅极电介质，其包括第一高k电介质材料，带隙破坏电介质，其包含具有与第一高k电介质不同带隙的电介质材料材料和包含第二高k电介质材料的第二高k栅极电介质。带隙破坏电介质包括介电材料的至少一个连续的原子层。因此，分层栅极电介质堆叠包括第一高k栅极电介质和带隙破坏电介质之间的第一原子界面，以及第二高k栅极电介质和带隙破坏电介质之间的第二原子界面其与带隙破坏电介质的电介质材料的至少一个连续原子层与第一原子界面间隔开。带隙干扰介质的插入导致较低的栅极泄漏，而不会导致阈值电压特性和有效氧化物厚度的任何实质性变化。

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