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21. 发明申请

US20070275510A1 METAL OXIDE FIELD EFFECT TRANSISTOR WITH A SHARP HALO AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有夏普HALO的金属氧化物场效应晶体管和形成晶体管的方法
公开(公告)号：US20070275510A1
公开(公告)日：2007-11-29
申请号：US11420318
申请日：2006-05-25
申请人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
发明人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
IPC分类号： H01L21/8232 , H01L21/8234 , H01L21/335
CPC分类号： H01L29/66636 , H01L29/6659 , H01L29/7833
摘要： Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.
摘要翻译：公开了具有限定的限定的卤素的MOSFET的实施例，其限定的源极/漏极扩展部分以及形成MOSFET的方法。蚀刻半导体层以形成切割栅极介电层的凹部。低能量植入物形成晕轮。然后，执行COR预清洁，并且通过外延沉积填充凹部。外延可以被原位掺杂或随后植入以形成源/漏扩展。或者，蚀刻之后紧接着是COR预清洁，随后进行外延沉积以填充凹部。在外延沉积工艺期间，沉积的材料被掺杂以形成原位掺杂的光晕，然后切换掺杂剂以形成邻近光晕的原位掺杂的源极/漏极延伸。或者，在形成原位掺杂的光晕之后，进行沉积工艺而没有掺杂剂，并且使用注入来形成源极/漏极延伸部。

22. 发明授权

US07256399B2 Non-destructive in-situ elemental profiling 失效
标题翻译：非破坏性原位元素分析
公开(公告)号：US07256399B2
公开(公告)日：2007-08-14
申请号：US10907591
申请日：2005-04-07
申请人： Siddhartha Panda , Michael R. Sievers , Richard S. Wise
发明人： Siddhartha Panda , Michael R. Sievers , Richard S. Wise
IPC分类号： G01N23/227
CPC分类号： G01N23/2273
摘要： A non-destructive in-situ elemental profiling of a layer in a set of layers method and system are disclosed. In one embodiment, a first emission of a plurality of photoelectrons is caused from the layer to be elementally profiled. An elemental profile of the layer is determined based on the emission. In another embodiment, a second emission of a plurality of photoelectrons is also received from the layer, and an elemental profile is determined by comparison of the resulting signals. A process that is altering the layer can then be controlled “on-the-fly” to obtain a desired material composition. Since the method can be employed in-situ and is non-destructive, it reduces turn around time and lowers wafer consumption. The invention also records the composition of all processed wafers, hence, removing the conventional statistical sampling problem.
摘要翻译：公开了一组层中的层的非破坏性原位元素分析方法和系统。在一个实施例中，多个光电子的第一次发射是从该层进行元素分析。基于发射确定层的元素分布。在另一个实施例中，也从该层接收多个光电子的第二次发射，并且通过比较所得到的信号来确定元素分布。然后可以“即时”控制改变层的方法以获得所需的材料组成。由于该方法可以原位使用并且是非破坏性的，所以可以减少周转时间并降低晶片消耗。本发明还记录了所有加工晶片的组成，因此，去除了常规统计抽样问题。

23. 发明授权

US08580628B2 Integrated circuit contact structure and method 有权
标题翻译：集成电路接触结构及方法
公开(公告)号：US08580628B2
公开(公告)日：2013-11-12
申请号：US13365030
申请日：2012-02-02
申请人： André P. Labonté , Richard S. Wise , Ying Li , Brett H. Engel
发明人： André P. Labonté , Richard S. Wise , Ying Li , Brett H. Engel
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/76834 , H01L21/823828 , H01L21/823871 , H01L29/66545
摘要： An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact.
摘要翻译：具有不对准容限的电接触的集成电路是通过提供半导体衬底形成的，其上是由第一介电区横向界定的第一FET栅极，用第二电介质区域代替第一FET栅极的上部，施加掩模，其具有部分地在所述衬底的相邻源极或漏极接触区域上方延伸的开口以及在所述第一FET栅极上方的所述第二电介质区域的一部分上方，形成穿过延伸到所述接触区域的所述第一电介质区域的开口，第二电介质区域，并且用与该接触区域电连接但与第一FET栅极与第二电介质区域电绝缘的导体填充该开口。还可以提供另外的FET栅极，其具有与源极 - 漏极触点分开形成的电接触。

24. 发明授权

US08436427B2 Dual metal and dual dielectric integration for metal high-K FETs 有权
标题翻译：金属高K FET双金属和双电介质集成
公开(公告)号：US08436427B2
公开(公告)日：2013-05-07
申请号：US13080962
申请日：2011-04-06
申请人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
发明人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L27/092
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/49 , H01L29/7833
摘要： The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
摘要翻译：在一个实施例中，本发明提供一种形成半导体器件的方法，该半导体器件包括提供包括第一导电类型区域和第二导电类型区域的衬底; 在所述基板的第一导电类型区域和所述第二导电类型区域之上形成包括栅极电介质的栅极堆叠和覆盖所述高k栅极电介质的第一金属栅极导体; 去除存在于第一导电类型区域中的第一金属栅极导体的一部分以暴露存在于第一导电类型区域中的栅极电介质; 将氮基等离子体施加到所述基板，其中所述氮基等离子体氮化存在于所述第一导电类型区域中的所述栅极电介质，并且氮化所述第二导电类型区域中存在的所述第一金属栅极导体; 以及形成覆盖存在于第一导电类型区域中的至少栅极电介质的第二金属栅极导体。

25. 发明申请

US20120190203A1 METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION 有权
标题翻译：用于高密度等离子体化学蒸气沉积的方法和装置
公开(公告)号：US20120190203A1
公开(公告)日：2012-07-26
申请号：US13434934
申请日：2012-03-30
申请人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
发明人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
IPC分类号： H01L21/311
CPC分类号： C23C16/507 , C23C16/345 , C23C16/402 , C23C16/45578 , C23C16/4586 , C23C16/56 , H01J37/20 , H01J37/321 , H01J2237/20207 , H01J2237/3323 , H01L21/31608 , H01L21/3185 , H01L27/10867
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

26. 发明授权

US07820555B2 Method of patterning multilayer metal gate structures for CMOS devices 有权
标题翻译： CMOS器件的多层金属栅极结构图形化方法
公开(公告)号：US07820555B2
公开(公告)日：2010-10-26
申请号：US11870577
申请日：2007-10-11
申请人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/823828 , H01L29/4966 , H01L29/51
摘要： A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.
摘要翻译：形成用于互补金属氧化物半导体（CMOS）器件的图案化多层金属栅极结构的方法包括执行第一蚀刻工艺以去除包括在栅极堆叠内的多晶硅层的暴露部分，形成在也包括在栅极堆叠内的金属层上的多晶硅层门堆在第一蚀刻工艺之后氧化暴露的金属层的顶部部分，以便产生相对于多晶硅层具有蚀刻选择性的金属氧化物层; 通过物理离子轰击的组合除去金属氧化物层，并向其中引入各向同性化学成分，以防止多晶硅层底角的氧化物质; 以及执行第二蚀刻工艺以去除所述金属层的暴露部分。

27. 发明申请

US20090098737A1 METHOD OF PATTERNING MULTILAYER METAL GATE STRUCTURES FOR CMOS DEVICES 有权
标题翻译：用于CMOS器件的多层金属栅结构的方法
公开(公告)号：US20090098737A1
公开(公告)日：2009-04-16
申请号：US11870577
申请日：2007-10-11
申请人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/461
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/823828 , H01L29/4966 , H01L29/51
摘要： A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.
摘要翻译：形成用于互补金属氧化物半导体（CMOS）器件的图案化多层金属栅极结构的方法包括执行第一蚀刻工艺以去除包括在栅极堆叠内的多晶硅层的暴露部分，形成在也包括在栅极堆叠内的金属层上的多晶硅层门堆在第一蚀刻工艺之后氧化暴露的金属层的顶部部分，以便产生相对于多晶硅层具有蚀刻选择性的金属氧化物层; 通过物理离子轰击的组合除去金属氧化物层，并向其中引入各向同性化学成分，以防止多晶硅层底角的氧化物质; 以及执行第二蚀刻工艺以去除所述金属层的暴露部分。

28. 发明授权

US07476578B1 Process for finFET spacer formation 有权
标题翻译： finFET间隔物形成工艺
公开(公告)号：US07476578B1
公开(公告)日：2009-01-13
申请号：US11776710
申请日：2007-07-12
申请人： Kangguo Cheng , Xi Li , Richard S. Wise
发明人： Kangguo Cheng , Xi Li , Richard S. Wise
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L29/785
摘要： A process for finFET spacer formation generally includes depositing, in order, a conformal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure.
摘要翻译：用于finFET间隔物形成的方法通常包括依次将共形衬垫材料，共形隔离材料和保形封盖材料沉积到finFET结构上; 倾斜地将掺杂剂离子注入围绕栅极结构的覆盖层的部分; 围绕源极和漏极区域选择性地去除未掺杂的封盖材料; 选择性地去除间隔物材料的暴露部分; 选择性地去除封盖材料的暴露部分; 各向异性地去除间隔物材料的一部分，以露出栅极材料的顶表面并将间隔物材料隔离到栅极结构的侧壁; 以及从翅片上去除氧化物衬垫以在finFET结构上形成间隔物。

29. 发明申请

US20080118955A1 METHOD FOR PRECISE TEMPERATURE CYCLING IN CHEMICAL / BIOCHEMICAL PROCESSES 审中-公开
标题翻译：化学/生化过程中精确循环的方法
公开(公告)号：US20080118955A1
公开(公告)日：2008-05-22
申请号：US11858280
申请日：2007-09-20
申请人： Siddhartha Panda , Richard S. Wise
发明人： Siddhartha Panda , Richard S. Wise
IPC分类号： C12P19/34 , B01J19/12
CPC分类号： C12Q1/686 , B01L7/52 , B01L7/5255 , B01L2300/1872 , C12Q2523/313
摘要： A method for implementing a temperature cycling operation for a biochemical sample to be reacted includes applying an infrared (IR) heating source to the biochemical sample to be reacted at a first infrared wavelength selected so as to generate a first desired temperature for a first duration and produce a first desired reaction within the biochemical sample; following the first desired reaction, applying the infrared (IR) heating source to the biochemical sample at a second infrared wavelength selected so as to generate a second desired temperature for a second duration and produce a second desired reaction within the biochemical sample; and wherein the first and second wavelengths generated by the IR source are selected to be coincident with corresponding absorptive wavelengths of the biochemical sample so as to heat the biochemical sample without directly heating a fluid medium containing the biochemical sample.
摘要翻译：用于实施待反应的生物化学样品的温度循环操作的方法包括将红外（IR）加热源施加到生物化学样品以在被选择的第一红外波长处反应，以便产生第一期望的第一期望温度，以及在生物化学样品中产生第一个所需的反应; 在第一期望的反应之后，以选择的第二红外波长将红外（IR）加热源施加到生物化学样品，以产生第二期望的第二期望温度，并在生化试样中产生第二所需反应; 并且其中由IR源产生的第一和第二波长被选择为与生物化学样品的相应吸收波长一致，以便加热生化样品而不直接加热含有生物化学样品的流体介质。

30. 发明授权

US06953724B2 Self-limited metal recess for deep trench metal fill 失效
标题翻译：用于深沟槽金属填充的自限制金属凹槽
公开(公告)号：US06953724B2
公开(公告)日：2005-10-11
申请号：US10605362
申请日：2003-09-25
申请人： Nikki L. Edleman , Richard S. Wise
发明人： Nikki L. Edleman , Richard S. Wise
IPC分类号： H01L21/285 , H01L21/3213 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10861 , H01L21/28568 , H01L21/32136
摘要： Disclosed is a method of manufacturing a deep trench capacitor structure that forms a trench in a substrate, lines the trench with a polysilicon liner, and forms titanium nitride columns along the polysilicon liner. The method etches the titanium nitride columns using chlorine-based dry chemistry that is substantially isotropic. This etching process removes the upper portion of the titanium nitride columns without affecting the polysilicon liner. The etching process attacks only in the uppermost portion of the titanium nitride columns such that, after the etching process is completed, the remaining lower portions of the titanium nitride columns are substantially unaffected by the etching process. Then, the method fills the space between the titanium nitride columns and the upper portion of the trench with additional polysilicon material. The process of filling the space simultaneously forms a polysilicon plug and polysilicon cap.
摘要翻译：公开了一种制造深沟槽电容器结构的方法，其在衬底中形成沟槽，用多晶硅衬垫对沟槽进行排列，并沿着多晶硅衬垫形成氮化钛柱。该方法使用基本上各向同性的氯基干化学法蚀刻氮化钛柱。该蚀刻工艺除去氮化钛柱的上部，而不会影响多晶硅衬垫。蚀刻工艺仅在氮化钛柱的最上部进行攻击，使得在蚀刻工艺完成之后，氮化钛柱的其余下部基本上不受蚀刻工艺的影响。然后，该方法用附加的多晶硅材料填充氮化钛柱和沟槽的上部之间的空间。同时填充空间的过程形成多晶硅插塞和多晶硅盖。

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