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21. 发明专利

JPS63239692A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63239692A
公开(公告)日：1988-10-05
申请号：JP7150587
申请日：1987-03-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MUKODA HIDEFUMI , TERASAWA MASAAKI , IKEDA TAISUKE , NAGAI YOSHIKAZU , SATO NOBUYUKI , FURUSAWA KAZUNORI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/02
摘要： PURPOSE:To shorten a time required for a reliability test relating to rapid rewriting or data holding characteristics at the time of system operation by controlling the supplying time of a rewriting voltage in response to control data set in a timer control means. CONSTITUTION:The titled device is provided with the timer control means TMCONT for programmably controlling the supplying time of rewriting voltages Vwr, Ver outputted from a rewrite control means WEC for supplying a voltage required for data rewriting to an electrically rewritable semiconductor non- volatile memory element based on control data stored in a prescribed semiconductor non-volatile memory element or control data supplied from the external through an exclusive pad not bonded by a wire. Since the supplying time of the rewriting voltages Vwr, Ver is controlled in response to the control data set in the timer control means TMCONT, the time of a reliability test relating to the rapid rewriting or data holding characteristics at the time of system operation can be shortened.

22. 发明专利

JPS634499A EEPROM DEVICE 失效
公开(公告)号：JPS634499A
公开(公告)日：1988-01-09
申请号：JP14698286
申请日：1986-06-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FURUSAWA KAZUNORI , TERASAWA MASAAKI , IKEDA TAISUKE , MUKODA HIDEFUMI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To improve a readout level margin by forming a readout reference voltage of a memory array by a dummy cell comprising a storage element receiving the reference potential and an address selection MOSFET. CONSTITUTION:The dummy cell consists of a MNOS transistor (TR) Q5, the address selection MOSFETQ4 and a separation MOSFETQ6. The gate of the address selection MOSFETQ4 is coupled with a 1st word line W11 corresponding thereto. Further, the gate of the MNOS TRQ5 has a threshold voltage of virgin level, then the threshold value is nearly a midpoint level of the MNOS TR at the write and erasure states. Thus, in order to keep the virgin level and in order to the write/erase in and from the MNOS TRQ5 forming the dummy cell, the gate is separated from a 2nd word line W112 corresponding thereto and connected to a ground potential of the circuit so as to always keep the state in the readout state.

23. 发明专利

JPS62197999A EEPROM DEVICE 失效
公开(公告)号：JPS62197999A
公开(公告)日：1987-09-01
申请号：JP3920586
申请日：1986-02-26
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATO NOBUYUKI , UJIIE KAZUAKI , FURUSAWA KAZUNORI , NABEYA SHINJI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To make an operation into high speed by switching the potential of a word line to which an MNOS is coupled to the high voltage of positive/ negative, according to a decode output signal. CONSTITUTION:In a write operation, when a control signal; the inverse of R/W goes to a low level temporarily, a MOSFET Q5 turns to an on-state, then outputting the high voltage like+12V in a high voltage terminal Vpp. Therefore, a MOSFET Q6 is made turn to an off-state, then the high voltage like +12V at the second word line W12, etc., being generated. Therefore, the high voltage like +12V functions between the gate of the MNOS coupled to the second word line W12 and the gate of a base board, and the write operation by the implantation of electric charge based on a tunnel phenomenon is performed.

24. 发明专利

JPS62165798A EEPROM DEVICE 失效
公开(公告)号：JPS62165798A
公开(公告)日：1987-07-22
申请号：JP646586
申请日：1986-01-17
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , SATO NOBUYUKI , UJIIE KAZUTOSHI , IKEDA TAISUKE , FURUSAWA KAZUNORI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06
摘要： PURPOSE:To speed up the read by providing a separation N-channel MOSFET to a data line so as to turn off at write operation. CONSTITUTION:Gates of separation MOSFETs Q3 or the like are connected in common to a control line to which a control voltage Vig is supplied, sources are used in common to constitute a common source line CS. The common source line CS is coupled to an output terminal of a common source line drive circuit DVR. The circuit DVR drives nearly to a power voltage VCC level to the line CS at erasure and the line CS is driven to a ground level nearly at the circuit at read operation. Thus, when a well WELL is brought into a power supply voltage VCC level at erasure, the forward bias of the junction between the electrode of the FET Q3 coupled to the line CS and the well WELL is prevented. Further, a current path required for the read is formed between the line CS and a ground point of the circuit. The MOSFETs Q7, Q8 are brought nearly into a low level close to zero voltage at the read and write.

25. 发明专利

JPS60152057A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60152057A
公开(公告)日：1985-08-10
申请号：JP721584
申请日：1984-01-20
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SATOU NOBUYUKI , TERASAWA MASAAKI , UCHIDA KEN , NABEYA SHINJI , HAGIWARA TAKAAKI , TANIDA YUUJI
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/06 , H01L29/788 , H01L29/792 , H01L29/866
摘要： PURPOSE:To obtain different reference voltage easily by constituting a semiconductor device as constant-voltage diodes having each different withstanding voltage by utilizing the different junction withstanding voltage of two kinds of diodes having junctions of different shapes manufactured through the same process. CONSTITUTION:With a diode D1, a junction between high concentration (N type and P type) regions can be formed to a beltlike section along a P type region 11 to a plane shape parallel with the surface of a substrate 1 while a junction between the high concentration (N type) region and a low concentration (P type) region can be formed to a section shallower than the junction between the high concentration regions to a plane shape parallel with the surface of the substrate 1. With a diode D2, a junction between high concentration (N type and P type) regions can be shaped to the section surrounding the side surface of a P region 12 while a junction between the high concentration (N type) region and a low concentration (P type) region can be formed on a plane parallel with the surface of the substrate 1 in a section deeper than the junction between high concentration. Breakdown voltage at a time when P-N junctions are reverse-biassed differs in the diodes D1 and D2.

26. 发明专利

JPS6047299A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6047299A
公开(公告)日：1985-03-14
申请号：JP15488283
申请日：1983-08-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAGIWARA TAKAAKI , TANIDA YUUJI , NABEYA SHINJI , TERASAWA MASAAKI , UJIIE KAZUSATO , SATOU NOBUYUKI
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
摘要： PURPOSE:To increase the number of rewriting times of a nonvolatile memory by providing a defect relieving means reading a content of a spare bit on a chip to relieve a defective bit. CONSTITUTION:If a defective bit is recognized from the result of comparison of a comparator 11, the process moves to the defect relieving process. That is, a control circuit 13 operates a defect relieve drive circuit 12. The circuit 12 is operated even by an external test signal 121. When the circuit 12 is operated, relieve information is written in the nonvolatile memory of the defect relieving circuit 10. The stored information is two; address of the defective bit and 1-bit storing the application of relieve. The address comparison system is used for the address storage system of the defective bit. A spare memory 2 is constituted as plural number or provided in the column direction. In selecting the spare memory 2, address inputs ADRA4-A10 are coincident with addresses ADR'a4-a10 stored in the defect relieve circuit 10 in the comparison circuit in Fig. 1, an output 104 goes to high level and the spare memory 2 is selected.

27. 发明专利

JPS6038798A CHARGE PUMP CIRCUIT 失效
公开(公告)号：JPS6038798A
公开(公告)日：1985-02-28
申请号：JP14497783
申请日：1983-08-10
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TERASAWA MASAAKI , NABEYA SHINJI , HAGIWARA TAKAAKI , TANIDA YUUJI , UJIIE KAZUSATO
IPC分类号： G11C16/06 , G11C17/00
摘要： PURPOSE:To prevent the occurrence of an undesired electric oscillation by supplying clock pulses to a capacitor, which constitutes a charge pump circuit, through a switch FF to prevent clock pulses from leaking to a signal line. CONSTITUTION:When a word line W12 is not selected and is in the low level, a switching MOSFETQ33 connected to a capacitor C of a charge pump circuit CP is turned off, and a clock pulse phiP is not supplied to the capacitor C. Consequently, the clock phiP to the word line W12 not supplied through the capacitor C and the gate capacity of a turned-off switching MOSFETQ31, and the leak of the clock pulse is prevented and an undesired oscillation of the potential on the word line is not generated. As the result, reduction of write or erase efficiency and degradation of information storage characteristics are prevented.

28. 发明专利

JPS59112639A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS59112639A
公开(公告)日：1984-06-29
申请号：JP22168382
申请日：1982-12-17
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HAGIWARA TAKAAKI , TERASAWA MASAAKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L29/788 , H01L29/792 , H02M3/07
CPC分类号： H02M3/073
摘要： PURPOSE:To operate an IC which employs a plurality of types of power source voltages completely by a sole external power source by providing at least one respective generation sources of DC voltages higher and lower than the external power source in the IC. CONSTITUTION:A diode and a capacitor are connected in series in multiple stages, 5V is applied to a terminal, 0V is applied to a terminal 22, 5V is applied to a terminal 23. Then, a nodal point A is charged to the threshold voltage of a transistor to become 4V, and the nodal point B becomes 5V. When the terminal 22 is set to 5V and the terminal 23 is set to 0V, the point A becomes 5V and the point B is discharged to 4V. When the terminal 22 is again set to 0V and the terminal 23 is set to 5V, the point A is lowered to 4V, the point B is raised to 4+5=9V, and approx. 15V is obtained at an output 23 by three times repetition. When 5V is applied to an input terminal with depletion type FET31 of approx. -3V of threshold value and a gate 33 is grounded, 3V is generated at the output 34. A circuit integrated with element necessary for a plurality of types of voltages by ultrafine MOS element can be operated by a sole external power source.
摘要翻译：目的：通过提供至少一个比IC中的外部电源高和低的直流电压的相应发电源，来操作由单独的外部电源完全采用多种类型的电源电压的IC。构成：将二极管和电容器分级串联连接多个级，5V端子加到端子上，0V施加到端子22上，5V端子被施加到端子23.然后将节点A充电到阈值电压的晶体管变为4V，节点B变为5V。当端子22设置为5V并且端子23设置为0V时，点A变为5V，点B放电至4V。当端子22再次设置为0V并且端子23设置为5V时，点A降低到4V，点B升高到4 + 5 = 9V， 15V在输出23处获得三次重复。当5V施加到耗尽型FET31的输入端时， -3V的阈值和栅极33接地，在输出34产生3V。通过超细MOS元件与多种类型的电压所需的元件集成的电路可以由唯一的外部电源来操作。

29. 发明专利

JPH06251590A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06251590A
公开(公告)日：1994-09-09
申请号：JP3532593
申请日：1993-02-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KURODA KENICHI , TERASAWA MASAAKI
IPC分类号： G11C17/00 , G11C11/407 , G11C16/06 , H01L21/8247 , H01L27/115
摘要： PURPOSE:To obtain a semiconductor integrated circuit device which has a smaller memory size and an improved degree of memory integration by changing the arrangement of a word line driving circuit. CONSTITUTION:In an EPROM or a flash EPROM which are provided with nonvolatile memories capable of electrical writing/reading, a memory mat is made of plural word lines W0 to W3, plural data lines D0 to D3 and plural non-volatile memories Q00-Q33 provided at the cross points of these word lines and data lines. Word line driving circuits WD0 and WD2, which drive even numbered word lines W0 and W2, are placed between one end section of the word lines W0 and W2 and an X decoder. On the other hand word line driving circuits WD1 and WD3, which drive odd numbered word lines W1 and W3, are placed at the other end section of the word lines W1 and W3.

30. 发明专利

JPH05325573A FLASH MEMORY AND DATA PROCESSOR 失效
公开(公告)号：JPH05325573A
公开(公告)日：1993-12-10
申请号：JP1809593
申请日：1993-01-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIBA KAZUYOSHI , TERASAWA MASAAKI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06
摘要： PURPOSE:To provide a flash memory whose memory cells can be made uniform in erasure characteristics even if memory cells which share a source have variance in source coupling capacity. CONSTITUTION:A couple of memory cells Q21 and Q31 share the source S1 of a flash memory cell; and only one memory cell is erased and then the other memory cell is erased. Namely, memory cells in an even-numbered row A2 are erased and memory cells in an odd--numbered row A3 are erased. While the even-numbered row is erased, an erasure preventing voltage is applied to the odd-numbered row and while the odd-numbered row is erased, the erasure preventing voltage is applied to the even-numbered row. Consequently, a difference in the capacity coupling ratio between the source between the couple of memory cells and a floating gate can be ignored.

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