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21. 发明公开

EP0676764A3 A semiconductor integrated circuit. 失效
标题翻译：一种半导体集成电路。
公开(公告)号：EP0676764A3
公开(公告)日：1998-05-06
申请号：EP95302121
申请日：1995-03-29
申请人： HITACHI LTD
发明人： WATANABE TAKAO , NAKAGOME YOSHINOBU , ISHIKURA KAZUO , NAKAGAWA TETSUYA , KIUCHI ATSUSHI
IPC分类号： G06T1/20 , G06F13/00 , G06F15/167 , G06F15/80 , G06F17/10 , G06F17/15 , G06T5/20 , G11C7/10 , G11C7/00
CPC分类号： G11C7/1006 , G06F17/10 , G06F17/15 , G06K9/4642
摘要： Herein disclosed is a semiconductor integrated circuit capable of executing processing operations using two-dimensional data in a high parallelism and at a high speed.
The semiconductor integrated circuit comprises: a two-dimensional memory array (MAR); a parallel data transfer circuit (TRC) for transferring the data read out in parallel through data lines, in parallel to a processing circuit group by selecting the word lines of the two-dimensional memory array; and the processing circuit group (PE) for executing processing operations in parallel by using the data transferred from said parallel data transfer circuit. Each of the processing circuits can make access to the plurality of series word lines of said two-dimensional memory array and the data lines through the parallel data transfer circuit, and the data lines of the two-dimensional memory array, to which a plurality of adjoining processing circuits can make access, have an overlapped range.
Since the data lines of the two-dimensional memory array, to which the adjoining processing circuits can make access, have an overlapped range, the convolution processing operations or the like can be ex ecuted in parallel for the two-dimensional data stored in the two-dimensional memory array.

22. 发明专利

JP2003318771A Wireless communication device and microcomputer 有权
标题翻译：无线通信设备和微型计算机
公开(公告)号：JP2003318771A
公开(公告)日：2003-11-07
申请号：JP2002125685
申请日：2002-04-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KOJIMA KOJI , KIUCHI ATSUSHI , TAKIJIYO YUICHI , YAMAMOTO KATSUMI
IPC分类号： H04B1/16 , H04B1/40 , H04L7/00 , H04L12/28 , H04M1/725 , H04W52/02 , H04W56/00 , H04W84/10 , H04W84/12
CPC分类号： H04M1/7253 , H04W52/0287 , H04W84/18 , H04W88/02 , Y02D70/00 , Y02D70/142 , Y02D70/144 , Y02D70/20
摘要： PROBLEM TO BE SOLVED: To provide a wireless communication device, capable of restarting clock generation by a control of a baseband unit which operates on the same clock as that used by a high-frequency unit at a stop of clock generation, and capable of easily matching the timing of the restart of the clock generation and a timing of other operations, using the same common reference clock.
SOLUTION: The device has the high-frequency unit (10) for generating a first clock signal (CLK1) and the baseband unit (11). The baseband unit 11 is designed to generate a second clock signal (CLK2), for controlling a start/stop operation of generating the first clock signal, of perform data processing and clock counting by using the second clock signal, and to perform a timer operation and a time counting operation by using the second clock signal under the condition of low power consumption, after stopping the generation of the first clock signal. The baseband unit 11 can generate the start timing of generation of the first clock signal CLK1 by a timer operation, using the second clock signal CLK2.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种无线通信装置，其能够通过在与时钟生成停止时在与高频单元相同的时钟工作的基带单元的控制下重新开始时钟生成，以及能够使用相同的公共参考时钟容易地匹配时钟生成的重新启动的定时和其他操作的定时。解决方案：该装置具有用于产生第一时钟信号（CLK1）和基带单元（11）的高频单元（10）。基带单元11被设计成产生第二时钟信号（CLK2），用于通过使用第二时钟信号来控制产生第一时钟信号的开始/停止操作，执行数据处理和时钟计数，并且执行定时器操作以及在停止产生第一时钟信号之后，在低功耗的条件下使用第二时钟信号的时间计数操作。基带单元11可以使用第二时钟信号CLK2通过定时器操作生成产生第一时钟信号CLK1的开始定时。版权所有（C）2004，JPO

23. 发明专利

JP2000082009A DATA PROCESSOR 失效
公开(公告)号：JP2000082009A
公开(公告)日：2000-03-21
申请号：JP25072998
申请日：1998-09-04
申请人： HITACHI LTD
发明人： MURAKAMI YASUYUKI , KIUCHI ATSUSHI
IPC分类号： G06F12/04
摘要： PROBLEM TO BE SOLVED: To provide the data processor which can switch endians during operation in a system where a big endian and a little endian are both prevent. SOLUTION: The processor has an arithmetic control means 110 which recognizes the byte order of a word in 1st, word order and is provided with an alignment means which is connected to the arithmetic control means 110 and can selectively switch the byte order of an output word to an input word between 1st word order and 2nd word order, and instructs the 1st word order or 2nd word order to the alignment means. Interruption control means 180 and 181 varies the value of a flag means 182 182 after saving the value of the flag means 182 in response to a specific interruption to the arithmetic control means, and reloads the saved value to the flag means 182 in response to a recovery from the interruption.

24. 发明专利

JPH11175339A MICROCOMPUTER 失效
公开(公告)号：JPH11175339A
公开(公告)日：1999-07-02
申请号：JP34752797
申请日：1997-12-17
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , NAKAGAWA TETSUYA
IPC分类号： G06F7/00 , G06F9/318 , G06F9/38 , G06F12/02 , G06F15/16 , G06F15/80
摘要： PROBLEM TO BE SOLVED: To supply source data without any delay while holding the consistency between independent arithmetic operation and parallel arithmetic operation on an instruction system by providing a 1st and a 2nd operation mode, supplying data from a 1st and a 2nd memory to a 1st and a 2nd arithmetic circuit under specific conditions, and performing arithmetic operation. SOLUTION: A CPU 1, the 1st and 2nd memories MEMs 11 and 12, and the 1st and 2nd data arithmetic circuits EX11 and EX12 are constituted on the same semiconductor substrate. In the 1st operation mode, data are supplied from one of the 1st and 2nd memories MEM11 and MEM12 to the 1st data arithmetic circuit EX11, arithmetic operation is performed by the 1st data arithmetic circuit EX11, and the 2nd data arithmetic circuit EX12 stops operating. In the 2nd operation mode, data are supplied from the 1st memory MEM11 to the 1st data arithmetic circuit EX11, data are supplied from the 2nd memory MEM12 to the 2nd data arithmetic circuit EX12, and the 1st and 2nd data arithmetic circuits EX11 and EX12 performs arithmetic operation.

25. 发明专利

JPH09171454A DATA PROCESSOR 失效
公开(公告)号：JPH09171454A
公开(公告)日：1997-06-30
申请号：JP23614096
申请日：1996-09-06
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , HATANO YUJI , UMAJI TORU , NOGUCHI YOSHIKI , AKAO YASUSHI , BABA SHIRO
IPC分类号： G06F5/01 , G06F7/00 , G06F7/76 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38 , G06F15/78 , G06F17/10
摘要： PROBLEM TO BE SOLVED: To enable more complicated digital signal processing by constituting a digital signal processing unit so as to handle fixed point data. SOLUTION: A CPU 100 and a digital signal processing unit 104 whose operation is controlled by decoding an instruction by this CPU 100 are provided on a semiconductor substrate. This digital signal processing unit 104 has a function processing fixed point data. Namely, the arithmetic logical computing element 105 of this digital signal processing unit 104 executes addition/ subtraction and a logical arithmetic processing. A multiplier 106 multiplies two word data of 16-bit length and outputs the result of a 32-bit length. Further, in the case of an integral multiplication, the low rank word of a source register is inputted as source data, and in the case of a fixed point multiplication, the high rank of the source register is inputted as source data.

26. 发明专利

JPH07168697A CIRCUIT AND METHOD FOR DOUBLE-PRECISION DIVISION 失效
公开(公告)号：JPH07168697A
公开(公告)日：1995-07-04
申请号：JP22377994
申请日：1994-09-19
申请人： HITACHI LTD
发明人： NAKAGAWA TETSUYA , KIUCHI ATSUSHI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535
摘要： PURPOSE:To efficiently perform double-precision division by providing plural data registers which stores 2N data bit values respectively and an arithmetic and logical unit which has a shift circuit for data received at a two-input port. CONSTITUTION:An arithmetic execution device 1700 has X- and Y-data buses 1102 and 1104 and also includes the arithmetic and logical unit(ALU) 1712 having eight registers 1702-1709 constituting one set and the input shifter 1752 for the data received at the two-input port. Further, the circuit consists of an exclusive OR gate 1963 and an inverter 106 which calculate one quotient bit QB and a next ALU operation command bit QOP, a QB register 1674-6 and a QOP register 1674-7 which store QOP and QB bits generated in each instruction cycle of division, and a bit processor (BPU) which shifts QB bits generated in a precedent instruction cycle to the output register in each instruction cycle. The operation is performed by executing three specific division instructions.

27. 发明专利

JPH03147026A INFORMATION PROCESSOR 失效
公开(公告)号：JPH03147026A
公开(公告)日：1991-06-24
申请号：JP28296389
申请日：1989-11-01
申请人： HITACHI LTD
发明人： NAKAGAWA TETSUYA , KIUCHI ATSUSHI , UBUSAWA MITSURU
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To speed up an interruption processing by saving the contents of general purpose registers in a data memory when a decoded instruction is prescribed information, and saving them in registers for saving when it is not prescribed information. CONSTITUTION:The general purpose registers (processor register) R0-R3 which respectively have a register for saving S0-S3, the data memory 3 and a computing element 5 are respectively connected to a data bus 12, and a mass memory stack is provided on the memory 3 by using a memory stack pointer 4. When a control signal 9 decoded in an instruction decoder 6 is prescribed information, the contents of the registers R0-R3 are saved. When they are not prescribed information, the contents are saved in the registers S0-S3.

28. 发明专利

JPH03131924A INFORMATION PROCESSOR 失效
公开(公告)号：JPH03131924A
公开(公告)日：1991-06-05
申请号：JP26893189
申请日：1989-10-18
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , UMAJI TORU , NAKAGAWA TETSUYA
IPC分类号： G06F7/00
摘要： PURPOSE:To accurately execute the mutual conversion of data formats and to continue software property while holding interchangeability with a conventional kind of machine by adding a means for holding information indicating the attribute of data stored in a data holding means. CONSTITUTION:Data inputted from an external I/O pin 710 to a register 708 are stored in a data RAM 702 and multiplied by coefficient data stored in a coefficient ROM 701 by a floating decimal point multiplier 703 and the multiplied value is stored in a register 704. The data of the register 704 are multiplied by a floating decimal point multiplier 705, the multiplied value is accumulated on the data stored in an accumulator 706 and an attribute bit part 101 is added to data obtained by conversion processing from a reference data format into an internal data format. Specific functions at least such as positive infinity and negative infinity expressed by plural flags are included in the information indicating the attribute of the bit part 101 and the flags are also automatically updated in accordance with the updating of the data. Consequently, the mutual conversion of plural different data formats can be surely attained while holding the interchangeability with conventional functions.

29. 发明专利

JPH0371275A METHOD AND DEVICE FOR IMAGE TRANSFORMATION 失效
公开(公告)号：JPH0371275A
公开(公告)日：1991-03-27
申请号：JP20677189
申请日：1989-08-11
申请人： HITACHI LTD
发明人： NAKAGAWA TETSUYA , UMAJI TORU , KIUCHI ATSUSHI
IPC分类号： G09G5/36 , G06T3/00
摘要： PURPOSE:To easily execute strict consideration based upon a sampling principle by adaptively executing the interpolation filtering processing and thinning filtering processing of input discrete data in both of two processing processes. CONSTITUTION:Processing for finding out respective grating point data on an intermediate image can be executed by resampling texture data by using the grating point interval between respective grating points on the intermediate image reversely formed on an one-dimensional texture data. Thereby, the consideration of folding distortion based upon the sampling principle can be attained in each grating point on the intermediate image. Thereby, when an ideal low pass filter (LPF) whose amplitude is '1' when cut-off frequency is

30. 发明专利

JP2002163242A DATA PROCESSING SYSTEM 失效
公开(公告)号：JP2002163242A
公开(公告)日：2002-06-07
申请号：JP2000357598
申请日：2000-11-24
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , FOGG ANDREW
IPC分类号： G06F15/177 , G06F13/362 , G06F15/167
摘要： PROBLEM TO BE SOLVED: To transfer the transferred data at high speed and with good efficiency to a shared memory in processing the data by a plurality of processors. SOLUTION: A transfer end detecting circuit 5 provided in this data processing system 1 outputs an interrupt request signal IRQ2 to a slave processor 3 when a master processor 2 gains a write access to a specified address a1 of the shared memory 6, and outputs an interrupt request signal IRQ1 to the master processor 2 when the slave processor 3 gains a write access to a specified address a2 of the shared memory 6, and storage of transferred data in the shared memory 6 is recognized by the master processor 2 or the slave processor 3 to which do not gain a right access. The master processor 2 or the slave processor 3 to which the interrupt request signals IRQ1, IRQ2 are input performs the operation of reading the data stored in the shared memory 6.

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