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1. 发明授权

US6434691B2 Cell phones with instruction pre-fetch buffers allocated to low bit address ranges and having validating flags 失效
标题翻译：具有分配给低位地址范围并具有验证标志的指令预取缓冲区的手机
公开(公告)号：US6434691B2
公开(公告)日：2002-08-13
申请号：US82418601
申请日：2001-04-03
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MURAKAMI YASUYUKI , MATSUI SHIGEZUMI , NISHIYAMA KUNIHIKO , KIUCHI ATSUSHI , TAKITSUNE YUICHI
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802
摘要： In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of instruction buffers, flags each specific to each of instruction buffers, and a buffer controller circuit. The buffer controller circuit may allocate one of specific values that plural lower bits of an instruction address may take to each of the instruction buffers, and prefetch instructions to the instruction buffers each corresponding to a respective addresses designated to by the plural lower bits, from the address following a predetermined fetch address. The constitution for instruction prefetch as above may be implemented in a simpler manner than the controlling structure using address tags of a cache memory or the controlling structure using read-write pointer based on the counter in FIFO buffers.
摘要翻译：为了简化与具有少量循环的程序一起使用并且具有几乎在线性和顺序地址中的指令的指令预取架构，根据本发明的用于控制外部存储器中的总线的总线控制器包括多个指令缓冲器每个特定于每个指令缓冲器的标志，以及缓冲器控制器电路。缓冲器控制器电路可以分配指令地址的多个低位可以对每个指令缓冲器执行的特定值中的一个，并且将预取指令分配给指令缓冲器，每个指令缓冲器对应于由多个低位指定的各个地址，地址遵循预定的提取地址。如上所述的用于指令预取的结构可以比使用高速缓冲存储器的地址标签的控制结构或基于FIFO缓冲器中的计数器的使用读写指针的控制结构更简单地实现。

2. 发明专利

JPH10111339A LSI INSPECTING DEVICE 失效
公开(公告)号：JPH10111339A
公开(公告)日：1998-04-28
申请号：JP26407296
申请日：1996-10-04
申请人： HITACHI LTD
发明人： MURAKAMI YASUYUKI , NAKAGAWA TETSUYA , KIUCHI ATSUSHI
IPC分类号： G01R31/26 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide an LSI inspecting device that can suppress a pattern memory to a minimum even to a large-scale LSI and can execute a connection test to an asynchronous circuit easily at a low cost. SOLUTION: An LSI inspecting device consists of an input-output device 204 for supplying common input-output signal to a reference LSI201 and an inspected LSI202, formed by the same design technique, from the same terminal, and a nonmatching detecting circuit 207 for comparing output signals of the reference LSI201 and inspected LSI202. In this case, a three-state buffer 208 is provided between the input-output device 204 and the inspected LSI201. An asynchronous signal generating circuit acting synchronously to the reference LSI201 is provided, and the nonmatching detecting circuit can judge matching/ nonmathing of output of both reference LSI201 and inspected LSI202 with fixed timing allowance.

3. 发明专利

JPH08251011A CMOS LOGIC CIRCUIT 失效
公开(公告)号：JPH08251011A
公开(公告)日：1996-09-27
申请号：JP5542395
申请日：1995-03-15
申请人： HITACHI LTD
发明人： MURAKAMI YASUYUKI , ONO KOICHI , HIRAKI MITSURU , MIKI YOSHIO , HATANO YUJI
IPC分类号： H03K19/018 , H03K19/0948
摘要： PURPOSE: To reduce the through current of a CMOS logic circuit. CONSTITUTION: This circuit includes an output wire 217 from a pMOS 211 to a load-side CMOS gate 202 between the drive-side pMOS 211 and drive-side nMOS 212 of a drive-side CMOS gate 201 and an output wire 218 from the end to the end of the gate electrode of the pMOS 221 or nMOS 222 of the load-side CMOS gate 211 and from a load-side CMOS gate 211 to an nMOS in series. Therefore, a delay circuit is considered to be interposed between the drive-side pMOS and drive-side nMOS, and a difference in output waveform is generated between the output terminal of the nMOS and pMOS output terminal to advance transition from 'ON' to 'OFF' of the pMOS or nMOS during this delay, so the through current is reduced. Further, the load-side CMOS gate has a difference between a pMOS gate input and an nMOS gate input, so both the pMOS and nMOS have delay in the direction wherein the time of 'ON' decreases, so the through current is further reduced.

4. 发明专利

JP2001312404A DATA PROCESSOR AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JP2001312404A
公开(公告)日：2001-11-09
申请号：JP2001027990
申请日：2001-02-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUI SHIGESUMI , MURAKAMI YASUYUKI , NISHIYAMA KUNIHIKO , KIUCHI ATSUSHI , TAKIJIYO YUICHI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To simplify the constitution of a instruction prefetch from a processing program which has nearly no loop instruction and in which instructions are arranged in linear successive addresses. SOLUTION: A bus controller +(4) which performs bus control over an external memory (2) is equipped with instruction buffers (Buf4, Buf8, and BufC), flags (Flg4, Flg8, and FlgC) intrinsic to the instruction buffers, and a buffer control circuit (30). The buffer control circuit allocates intrinsic values that low-order bits of an instruction address possibly have to the instruction buffers and prefetches instructions to the instruction buffers corresponding to the address order determined by the low-order bits from the address following a prescribed instruction fetch address as a starting point. The constitution for the instruction prefetch can be actualized simply by a control mechanism by the address tag of a cache memory and a read/write pointer control mechanism by the counter of a FIFO buffer.

5. 发明专利

JP2000082009A DATA PROCESSOR 失效
公开(公告)号：JP2000082009A
公开(公告)日：2000-03-21
申请号：JP25072998
申请日：1998-09-04
申请人： HITACHI LTD
发明人： MURAKAMI YASUYUKI , KIUCHI ATSUSHI
IPC分类号： G06F12/04
摘要： PROBLEM TO BE SOLVED: To provide the data processor which can switch endians during operation in a system where a big endian and a little endian are both prevent. SOLUTION: The processor has an arithmetic control means 110 which recognizes the byte order of a word in 1st, word order and is provided with an alignment means which is connected to the arithmetic control means 110 and can selectively switch the byte order of an output word to an input word between 1st word order and 2nd word order, and instructs the 1st word order or 2nd word order to the alignment means. Interruption control means 180 and 181 varies the value of a flag means 182 182 after saving the value of the flag means 182 in response to a specific interruption to the arithmetic control means, and reloads the saved value to the flag means 182 in response to a recovery from the interruption.

6. 发明专利

JPH0613959A METHOD FOR ELECTRIC FIELD STRENGTH DETECTION PROCEDURE CONTROL FOR MOBILE RADIO COMMUNICATION 失效
公开(公告)号：JPH0613959A
公开(公告)日：1994-01-21
申请号：JP16586792
申请日：1992-06-24
申请人： HITACHI LTD
发明人： OTSUKA MASANORI , HATANO YUJI , KIKUCHI TAKAFUMI , MURAKAMI YASUYUKI , HOTTA MASAO
IPC分类号： H04B7/26
摘要： PURPOSE:To reduce the power consumption by decelerating a speed of a trigger clock for setting interval of electric field strength measurement and omitting the measurement of the electric field strength when the electric field strength is remarkably high or its change is small. CONSTITUTION:When the electric field strength absolute value measurement mode is selected by the designation of a control processor 214, the processor 214 discriminates whether or not the electric field strength is at a threshold level or over to calculate a change in the electric field strength or to stop the calculation thereby deciding whether or not the speed of the trigger clock is decreased. When the electric field strength is not so much high, the electric field strength change calculation mode is selected, circuit comprising a register 210 and a subtracter 211 calculates a difference between a current signal and a signal of one preceding sample and the fluctuation in the electric field strength is obtained and it is inputted to the processor 214. When a change in the electric field strength is small, the trigger clock is decelerated. Thus, the frequency of the detection of the electric field strength in a base station for the mobile radio terminal equipment and the measurement of the electric field strength of an adjacent station is reduced.

7. 发明专利

JPH066426A DIGITAL TELEPHONY EQUIPMENT 失效
公开(公告)号：JPH066426A
公开(公告)日：1994-01-14
申请号：JP16454292
申请日：1992-06-23
申请人： HITACHI LTD
发明人： HATANO YUJI , OTSUKA MASANORI , KIKUCHI TAKAFUMI , MURAKAMI YASUYUKI , HOTTA MASAO
IPC分类号： H04M1/00 , H04M1/253
摘要： PURPOSE:To keep speaking even when the sound quality of voice encoding is adverse by feeding a synthetic voice decoding a parameter encoding a speaker voice back to the auditory sensation of a speaker as a sidetone. CONSTITUTION:A source voice input 301 from a microphone is sampled/ quantized by an A/D converter 302 and inputted to a voice encoder 303. The parameter of encoding is selected so as to minimize total weighting error between a synthetic voice p' (n) and an auditory sensation weightened input voice p (n.) At the same time, the synthetic voice p' (n) receives required band limiting through a post filter 304, afterwards, is superimposed to a voice output 311 decoding the received parameter as a sidetone 305 and becomes an input 313 of a speaker by a D/A converter 312. Since the sound quality of the encoded voice can be always grasped, the speaker makes required efforts such as clearly and slowly sounding or exchanging words so as to transmit required meanings naturally with the low sound quality.

8. 发明专利

JPH1139282A DATA PROCESSOR 失效
公开(公告)号：JPH1139282A
公开(公告)日：1999-02-12
申请号：JP19767497
申请日：1997-07-24
申请人： HITACHI LTD
发明人： MURAKAMI YASUYUKI , KIUCHI ATSUSHI , KAMIMAKI HARUO
IPC分类号： G06F7/53 , G06F7/52 , G06F7/523 , G06F17/10
摘要： PROBLEM TO BE SOLVED: To shorten the executing time of the calculation of (1+a)×b by using two source data. SOLUTION: A data processor respectively reads 32-bit data respectively containing 16-bit fixed-point data (a) and (b) from registers 122 and 123 which are designated by an instruction requesting the execution of the calculation of (1+a)×b and supplies the data (a) and (b) to a multiplier 130 by means of multiplexers 117 and 118 and the 32-bit data to an adder 132 through a one- bit left shifter 131 for adjusting the position of base point. The processor adds 16-bit '0' to the lower-rank side of the data (b) by means of a shifter 133 and supplies the obtained 32-bit data to the adder 132 through a selector 134. The adder 132 obtains the result data of the above-mentioned calculation. The result data are written in a register designated by the above instruction. The above calculation by means of the adder 132 and multiplier 130 is executed in one machine cycle. This arithmetic unit can execute the product-sum operation of a×b+c and multiplication of a×b by switching the operations of the selector 134.

9. 发明专利

JPH06324868A DIGITAL SIGNAL PROCESSOR WITH DEDICATED COMPUTING ELEMENT 失效
公开(公告)号：JPH06324868A
公开(公告)日：1994-11-25
申请号：JP11569293
申请日：1993-05-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURAKAMI YASUYUKI , HATANO YUJI , KAMIMAKI HARUO , MORISHIMA KENTA , HOTTA MASAO , ODAI KAZUO , ISHIDA JUN , ASAKAWA YOSHIAKI
IPC分类号： G06F9/38 , G06F13/28
摘要： PURPOSE:To reduce power consumption in an LSI as a whole by executing a part of simple processing which occupies the most part of algorithm as wired logic in which a dedicated computing element of scale smaller than that of a main computing element performs the transfer of data between data memory via a direct memory access(DMA) bus. CONSTITUTION:Such constitution is employed that the dedicated computing element 201 which performs limited processing on the algorithm is provided, and the dedicated computing element 201 is connected to the DMA buses 212, 212 connected to the data memory 104 and not being connected to the main computing element 106. In other words, the dedicated computing element 201 performs data transfer between the data memory 104 via the DMA buses 211, 212, which enables simple processing to be performed. The dedicated computing element 201 is a computing element of small scale provided with a limited computing function so as to be fitted in the execution of the simple processing. Therefore, it is possible to reduce the power consumption in the operation of the whole digital signal processor, i.e., the LSI in which the simple processing occupies the most part.

10. 发明专利

JPH06149295A SPEECH ENCODING PROCESSOR AND ITS METHOD 失效
公开(公告)号：JPH06149295A
公开(公告)日：1994-05-27
申请号：JP29957292
申请日：1992-11-10
申请人： HITACHI LTD
发明人： KAMIMAKI HARUO , HATANO YUJI , ASAKAWA YOSHIAKI , MURAMATSU RYUJIRO , SEKINE HIDETOSHI , MURAKAMI YASUYUKI
IPC分类号： G10L19/08 , G10L19/00 , H04B14/04 , G10L9/14 , G10L9/18
摘要： PURPOSE:To perform a CELP speech encoding processing which is sequential by plural processors which have high-speed processing capacity and to easily perform synchronization processing between the respective processors. CONSTITUTION:A master processor 1 performs the frame processing of speech data of one frame portion taken in from an A/D converter 3 and the processing result is transferred to a slave processor 2 along with the speech data. The slave processor 2 performs subordinate frame processing with the received speech data and frame processing result and outputs the result as encoded data to a transmitter 5. The data received by a receiver 6 are decoded by the master processor 1 after frame processing and outputted as a decoded speech to a D/A converter 4.

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