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21. 发明专利

JPH01296596A PLASMA X-RAY GENERATING DEVICE 失效
公开(公告)号：JPH01296596A
公开(公告)日：1989-11-29
申请号：JP12572088
申请日：1988-05-25
申请人： HITACHI LTD
发明人： SATO TOSHIHIKO , OCHIAI ISAO , KATO YASUO , OKAMOTO YUKIO , MURAYAMA SEIICHI
IPC分类号： H05G2/00 , H01J35/22 , H01L21/027 , H01L21/30 , H05G1/00
摘要： PURPOSE:To eliminate dispersion of X-ray intensity values and generated even creeping discharge with good reproducibility by attaching or embedding a conductor insulated in DC from inner and external conductors and coupled therewith in AC to the surface of or in an insulating body of a plasma X-ray generator device. CONSTITUTION:When a switch 6 is closed, positive polarity pulse voltage is applied to an inner conductor 1. This generates creeping discharge at the surface of an insulating body between a trigger electrode 11 and an outer conductor 2, which exerts the effect of preliminary disconnection, and an even creeping discharge is generated in such as way as wrapping the whole insulting body 3 to cause flow of a large current between the inner and outer conductors 1, 2. With this evenness held, the plasma is separated from the surface of the insulating body 3 by the magnetic pressure generated by this large current so as to form a disc-shaped plasma sheet, and when the tip of the inner conductor 1 is attained, self-compression heating is conducted to generate soft X-rays. To raise this self-compression heating properly, it is important to generate even creeping discharge, and therefore the trigger electrode 11 works effectively.

22. 发明专利

JPS61125050A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS61125050A
公开(公告)日：1986-06-12
申请号：JP24599284
申请日：1984-11-22
申请人： Hitachi Ltd
发明人： OKUYA KEN , SHIRAI MASAYUKI , YAMADA TAKEO , SATO TOSHIHIKO
IPC分类号： H01L21/60 , H01L21/92
CPC分类号： H01L24/81 , H01L2224/81801 , H01L2924/014
摘要： PURPOSE:To facilitate replacement of pellets, in a semiconductor device, in which electric connection is performed through bump electrodes, by the constitution, wherein one diameter of the bump electrode on the pallet side or the substrate side is made smaller than the other diameter. CONSTITUTION:In a pin-grid array type semiconductor device, a plurality of pellets are attached to a mother chip 7 that is attached on the upper surface of a substrate 2 through bump electrodes 10. A diameter d2 of the bump electrode 10 comprising solder 20 on the side of the pellet 9 is made smaller than a diameter d1 on the side of the mother chip 7, i.e., on the side of the substrate 2. When the pellet 9 is removed from the mother chip 7, the solder 20 is uniformly separated at a part close to the pellet. Therefore, the amount of the solder remaining on the side of the mother chip 7 becomes uniform and the replacement with the new pellets becomes easy. When the diameter of the bump 10 on the side of the pellet 9 is made larger than the diameter of one side of the mother chip 1 in the reverse mode to the above described procedure, the same effect is also obtained.
摘要翻译：目的：为了便于在通过突起电极进行电连接的半导体装置中，通过使托盘侧或基板侧的凸起电极的一个直径比另一直径小的结构来实现更换。构成：在针阵列型半导体器件中，多个粒料通过突起电极10附着在母片7上，母芯片7通过突起电极10附着在基片2的上表面上。凸块电极10的直径d2包括焊料20 使颗粒9的一侧比母芯片7侧的直径d1小，即在基板2侧。当将母粒9从母芯片7移除时，焊料20是均匀的在靠近颗粒的部分分离。因此，残留在母芯片7一侧的焊料的量变得均匀，并且用新的颗粒的更换变得容易。当以与上述步骤相反的方式使凸块10在丸粒9侧的直径大于母片1的一侧的直径时，也获得了相同的效果。

23. 发明专利

JP2008211251A Memory device 审中-公开
标题翻译：内存设备
公开(公告)号：JP2008211251A
公开(公告)日：2008-09-11
申请号：JP2008130515
申请日：2008-05-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAZATO KAZUO , ITO KIYOO , MIZUTA HIROSHI , SATO TOSHIHIKO , SHIMADA JUICHI , AHMED HAROON
IPC分类号： H01L21/8247 , G11C11/00 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a memory device having a tunnel barrier structure reduced in write, read and erase time. SOLUTION: The memory device has memory nodes 1 for writing an electric charge passed through a tunnel barrier structure 2 from a control electrode 9. The stored charges give an influence on the conductivity of a source-drain path 4. The conductivity of the path 4 is monitored to read data. The charge barrier structure is a multiple tunnel barrier structure which is composed by alternately laminating polysilicon layers 16 3 nm thick and Si 3 N 4 layers 15 1 nm thick, covering a polycrystal layer 1 of Si which forms the memory nodes 1, or may be a barrier structure 2 which includes a Schottky barrier structure and conductive nano-scale conductive islands 30, 36 and 44 dispersed in an electric insulation matrix for acting as the memory nodes. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在写入，读取和擦除时间上减少了隧道势垒结构的存储器件。解决方案：存储器件具有用于从控制电极9写入穿过隧道势垒结构2的电荷的存储器节点1.存储的电荷对源极 - 漏极路径4的导电性产生影响。导电性监视路径4以读取数据。电荷势垒结构是多层隧道势垒结构，其通过交替层叠13nm厚的多晶硅层和15nm厚的Si <3> / S> 4 层组成，覆盖多晶形成存储器节点1的Si层1，或者可以是阻挡结构2，其包括分散在用作存储器节点的电绝缘矩阵中的肖特基势垒结构和导电纳米级导电岛30,36和44。版权所有（C）2008，JPO＆INPIT

24. 发明专利

JP2004247756A Method of manufacturing single electron element 审中-公开
公开(公告)号：JP2004247756A
公开(公告)日：2004-09-02
申请号：JP2004129496
申请日：2004-04-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SATO TOSHIHIKO , SHIMADA JUICHI
IPC分类号： H01L29/06 , H01L29/66
CPC分类号： G11C2216/08
摘要： PROBLEM TO BE SOLVED: To provide a method where subjects present in a prior art are solved, for manufacturing in large quantities integrated single electron devices which have high operating temperatures and can be operated even at room temperature at high yields. SOLUTION: A particulate 120 which is a capture site of electrons preattached to the surface of an insulator layer 210 formed on the substrate 200 is re-disposed by using the probe of a scanning probe microscope such as AFM/STM, self systematic pattern formation capability is expressed by interactions with three categories largely classified into three kinds, namely, interaction between the particulate 120 and the substrate 200, interaction of the particulates 120 with each other and interaction between a third medium present in surroundings of, or between the substrate 200 and the particulate 120 and the particulate 120, to constitute the method for preparing the single electron device by collectively forming two micro-tunnel junctions or more on the substrate 200. COPYRIGHT: (C)2004,JPO&NCIPI

25. 发明专利

JP2002026073A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002026073A
公开(公告)日：2002-01-25
申请号：JP2000207496
申请日：2000-07-07
申请人： HITACHI LTD
发明人： SUMI YOSHIYUKI , KIKUCHI HIROSHI , YOSHIDA IKUO , SATO TOSHIHIKO
IPC分类号： H01L25/18 , H01L21/60 , H01L25/04
摘要： PROBLEM TO BE SOLVED: To provide mounting technology which is suitable to a chip which has many terminals as to a semiconductor device which has a chip mounted on a wiring board in the flip-chip way across bump electrodes. SOLUTION: On the main surface of a silicon chip 6A, solder bumps 8 are arranged in matrix. The gap between the silicon chip 6A and a module substrate 2 is filled with anisotropic conductive resin 10 and the solder bumps 8 and electrode pads 4 of the module substrate 2 are electrically connected through metal particles in the anisotropic conductive resin 10.

26. 发明专利

JP2000077554A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2000077554A
公开(公告)日：2000-03-14
申请号：JP24237098
申请日：1998-08-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ANDO HIDEKO , KIKUCHI HIROSHI , SATO TOSHIHIKO
IPC分类号： H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent harmful phenomena and to eliminate adverse effects on human health and environment by using lead-free solder bump which does not contain lead as a solder bump electrically for connecting a semiconductor chip to a package substrate. SOLUTION: For this semiconductor device, a solder bump 3 electrically connects a pad 1a formed as an external electrode on the surface of a semiconductor chip 1 to a pad 2a formed, as an external electrode on the surface of a package 2. As the solder bump 3, a lead-free solder bump which has a melting point at 250 deg.C or above and does not contain a lead, is used. As a result, since the solder bump 3 does not contain harmful lead, a harmful phenomena are prevented, and such conventional problems affecting human health and environment are prevented from occurring.
摘要翻译：要解决的问题：通过使用不含铅的无铅焊料作为用于将半导体芯片连接到封装基板的焊料凸块，来防止有害现象和消除对人体健康和环境的不利影响。解决方案：对于该半导体器件，焊料凸块3将形成为半导体芯片1的表面上的外部电极的焊盘1a电连接到在封装2的表面上形成的焊盘2a作为外部电极。作为焊料凸点3，使用熔点在250℃以上且不含引线的无铅焊料凸点。结果，由于焊锡凸块3不含有害铅，因此防止了有害现象，防止了影响人体健康和环境的传统问题。

27. 发明专利

JPH11232710A MAGNETIC MEMORY 失效
公开(公告)号：JPH11232710A
公开(公告)日：1999-08-27
申请号：JP2618698
申请日：1998-02-06
申请人： HITACHI LTD
发明人： NAKATANI RYOICHI , FUTAMOTO MASAAKI , INABA NOBUYUKI , SATO TOSHIHIKO
IPC分类号： G11C11/15 , G11B5/127 , G11B5/39 , G11B11/08 , G11B11/10 , G11B11/105 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a magnetic memory capable of surely recording in a specified memory cell without deleting information from a memory cell other than the memory cell for recording. SOLUTION: Memory cells 10a to 10c are composed of a multilayer film sequentially laminated with a magnetic layer 14 having a relatively low coercive force, a non-magnetic layer 13 and a magnetic layer 12 having a relatively high coercive force. After the specified memory cell 10c is heated by a laser light 19, by using a field applying mechanism 20 to apply a magnetic field at the time of cooling the memory cell 10c, information is recorded in the magnetic layer 12 having a relatively high coercive force.

28. 发明专利

JPH1168192A MULTI-TUNNEL JUNCTION, TUNNEL MAGNETORESISTANCE EFFECT ELEMENT, MAGNETIC SENSOR AND MAGNETIC RECORDING SENSOR HEAD 失效
公开(公告)号：JPH1168192A
公开(公告)日：1999-03-09
申请号：JP22150197
申请日：1997-08-18
申请人： HITACHI LTD
发明人： SATO TOSHIHIKO , NAKATANI RYOICHI , INABA NOBUYUKI
IPC分类号： G01R33/035 , G01R33/06 , G01R33/09 , G11B5/39 , G11C11/16 , H01F10/00 , H01F10/08 , H01F10/32 , H01L29/66 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To make operable at room temp. SOLUTION: On a substrate 11 composed of an insulator layer a first soft magnetic material-made layer 210 is formed, an insulation layer 350 is formed on the substrate 11 and soft magnetic layer 210, a first and second tunnel barrier layers 310, 311 made from dielectric films are formed on a region surrounded by the insulation layer 350 on the magnetic layer 210, ferroelectric particles 110 of 10 nm or less are provided between the tunnel barrier layers 310, 311, and a second soft magnetic material-made layer 211 is formed on the barrier layer 311.

29. 发明专利

JPH10199938A METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR 失效
公开(公告)号：JPH10199938A
公开(公告)日：1998-07-31
申请号：JP316297
申请日：1997-01-10
申请人： HITACHI LTD
发明人： SAKUMA MITSUHIRO , KIKUCHI HIROSHI , SATO TOSHIHIKO , HAYASHIDA TETSUYA
IPC分类号： H01L21/60 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To reduce the amt. of flux applied and prevent causing flux residues. SOLUTION: This manufacturing apparatus comprises a reflow furnace 2 for heat-treating a semiconductor integrated circuit device 3 having semiconductor elements 1 and element mounting board 4, and means 5 for forming a flux atmosphere 13 in the furnace 2. In the flux atmosphere 13 formed by this means 5, provisionally fixed bumps 6 are melted to electrically connect the elements 1 to the mounting board 4.

30. 发明专利

JPH10173107A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10173107A
公开(公告)日：1998-06-26
申请号：JP32740596
申请日：1996-12-09
申请人： HITACHI LTD
发明人： SAKUMA MITSUHIRO , KIKUCHI HIROSHI , MIYAMOTO SEIJI , SATO TOSHIHIKO , HAYASHIDA TETSUYA
IPC分类号： H01L23/12 , H01L23/32 , H05K3/30 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which prevents BGA balls of a package from crashing even if having a large-wt. heat radiation plate. SOLUTION: The semiconductor integrated circuit device has a package base 2 mounting an LSI chip 1; the package 2 being electrically connected to a printed board 4 through BGA balls 2a disposed at a lower part of the base 2. Pins 3 are disposed as spacers at the lower part of the package base 2, thereby adjusting the clearance between the package base 2 the and printed board 4 for a desired distance.

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