专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6433412B2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6433412B2
公开(公告)日：2002-08-13
申请号：US80058901
申请日：2001-03-08
申请人： HITACHI LTD
发明人： ANDO HIDEKO , KIKUCHI HIROSHI , YOSHIDA IKUO , SATO TOSHIHIKO , SHIMIZU TOMO
IPC分类号： H01L23/28 , H01L21/56 , H01L21/60 , H01L23/02 , H01L23/12 , H01L23/24 , H01L23/36 , H01L25/00 , H01L25/16
CPC分类号： H01L24/32 , H01L21/563 , H01L23/24 , H01L23/3135 , H01L24/29 , H01L25/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/27013 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73257 , H01L2224/83051 , H01L2224/83102 , H01L2224/92125 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/351 , H01L2924/00012 , H01L2224/13111 , H01L2924/00014 , H01L2924/0665 , H01L2924/00
摘要： A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 using face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions and for relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.
摘要翻译：封装基板2的主面的中心部分通过倒装芯片接合系统使用面朝下接合安装有存储芯片1。此外，在存储芯片1的附近安装多个芯片冷凝器7.将存储芯片1的主面（下表面）与封装基板2的主面之间的间隙填充有底部填充树脂（密封树脂）10构成用于实现对连接部分的保护和用于放松热应力的密封构件。底部填充树脂10的外边缘延伸到存储芯片1的外侧，并覆盖安装在存储芯片1附近的芯片电容器7的整个面。

2. 发明专利

DE4126963A1 Optical measuring system with frequency converter - producing pairs of photons from light source and followed by beam splitter 未知
公开(公告)号：DE4126963A1
公开(公告)日：1992-02-20
申请号：DE4126963
申请日：1991-08-14
申请人： HITACHI LTD
发明人： SATO TOSHIHIKO , MURAYAMA SEIICHI
IPC分类号： G01J1/16 , G01N21/17 , G01N21/31 , G01N21/65
摘要： A frequency converter (200) provides a pair of first (21) and second photons from the light source (100). A beam splitter (300) divides the beam path of the photon pair into a first beam path (41) into which the first photon are guided for leading into a sample (400) to be measured and a second beam path (31) through which the second photons are guided. A photodetector (501) in the first beam path (41,42) registers its light intensity. Another photodetector (502) has the same function for the second beam path (31). A subtraction circuit (600) extinguishes the quanta noise of the light source on the basis of the outputs of the photodetectors. A data processor (700) measures the optical quality of the sample on the basis of the output of the subtraction circuit. USE/ADVANTAGE - Almost any type of optical measuring system for quality control and material testing. Measuring samples for controlling contamination and biological systems used in industry, e.g. investigating output gas during semiconductor prodn. detecting dust in air of clean room, measuring attenuation coefft. of optical fibres, detecting micro-fissures in transparent materials, e.g. glass. Identifies very small amts. and changes in optical qualities. Suppresses quanta noise of light source.

3. 发明专利

CA2220782C MEMORY DEVICE WITH CHARGE STORAGE BARRIER STRUCTURE 未知
公开(公告)号：CA2220782C
公开(公告)日：2008-07-22
申请号：CA2220782
申请日：1997-11-12
申请人： HITACHI LTD
发明人： SHIMADA TOSHIKAZU , ITOH KIYOO , MIZUTA HIROSHI , SATO TOSHIHIKO , AHMED HAROON , NAKAZATO KAZUO
IPC分类号： H01L27/10 , H01L29/78 , G11C11/34 , G11C13/02 , G11C16/02 , H01L21/28 , H01L21/8232 , H01L21/8239 , H01L27/105 , H01L29/06 , H01L29/51 , H01L29/772 , H01L29/786 , H01L29/788
摘要： A memory device includes a memory node (1) to which charge is written throug h a tunnel barrier configuration (2) from a control electrode (9). The stored ch argeeffects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multi ple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3nm thickness and layers (15) of Si3N4 of 1nm thickness, over lying polycrystalline layer of silicon (1) which forms the memory node. Alternativ e barrier configurations (2) are described, including a Schottky barrier confi guration, and conducive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

4. 发明专利

AU736388B2 Memory device 未知
公开(公告)号：AU736388B2
公开(公告)日：2001-07-26
申请号：AU4360597
申请日：1997-10-29
申请人： HITACHI LTD
发明人： NAKAZOTO KAZUO , ITOH KIYOO , MIZUTA HIROSHI , SATO TOSHIHIKO , SHIMADA TOSHIKAZU , AHMED HAROON
IPC分类号： H01L29/78 , G11C13/02 , G11C16/02 , H01L21/28 , H01L29/06 , H01L29/51 , H01L29/772 , H01L29/786 , H01L29/788 , H01L29/88 , H01L29/76 , H01L27/10
摘要： A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3nm thickness and layers (15) of Si3N4 of 1nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

5. 发明专利

HK1015936A1 Memory device 未知
公开(公告)号：HK1015936A1
公开(公告)日：1999-10-22
申请号：HK99100705
申请日：1999-02-22
申请人： HITACHI LTD
发明人： NAKAZATO KAZUO , ITOH KIYOO , MIZUTA HIROSHI , SATO TOSHIHIKO , SHIMADA TOSHIKAZU , AHMED HAROON
IPC分类号： G11C11/00 , G11C

6. 发明专利

AU4360597A Memory device 未知
公开(公告)号：AU4360597A
公开(公告)日：1998-05-21
申请号：AU4360597
申请日：1997-10-29
申请人： HITACHI LTD
发明人： NAKAZOTO KAZUO , ITOH KIYOO , MIZUTA HIROSHI , SATO TOSHIHIKO , SHIMADA TOSHIKAZU , AHMED HAROON
IPC分类号： H01L29/78 , G11C13/02 , G11C16/02 , H01L21/28 , H01L29/06 , H01L29/51 , H01L29/772 , H01L29/786 , H01L29/788 , H01L29/88 , H01L29/76 , H01L27/10
摘要： A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3nm thickness and layers (15) of Si3N4 of 1nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

7. 发明专利

CA2220782A1 MEMORY DEVICE 未知
公开(公告)号：CA2220782A1
公开(公告)日：1998-05-15
申请号：CA2220782
申请日：1997-11-12
申请人： HITACHI LTD
发明人： NAKAZATO KAZUO , AHMED HAROON , SHIMADA TOSHIKAZU , ITOH KIYOO , MIZUTA HIROSHI , SATO TOSHIHIKO
IPC分类号： H01L29/78 , G11C13/02 , G11C16/02 , H01L21/28 , H01L29/06 , H01L29/51 , H01L29/772 , H01L29/786 , H01L29/788 , H01L27/10 , H01L27/105 , G11C11/34 , H01L21/8232 , H01L21/8239
摘要： A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitori ng the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3nm thickness and layers (15) of Si3N4 of 1nm thickness, overlyin g polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configura tion, and conducive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

8. 发明专利

JP2001044307A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2001044307A
公开(公告)日：2001-02-16
申请号：JP21060599
申请日：1999-07-26
申请人： HITACHI LTD
发明人： MIYAMOTO SEIJI , ITO OSAMU , SATO TOSHIHIKO , HAYASHIDA TETSUYA
IPC分类号： H01L23/12 , H01L23/02 , H01L23/08 , H01L23/10
摘要： PROBLEM TO BE SOLVED: To improve reliability in airtightness and prevent breakage of wires in a chip support board. SOLUTION: A semiconductor device comprises a package board 2 for supporting a semiconductor chip 5, a measure-shaped cap member 6 for sealing the chip 5 while being jointed to the board 2, a sealing solder 7 for jointing the board 2 to the member 6, a cap-side metallized layer 6a provided on a joint surface 6b of the member 6 for jointing with the solder 7, and a board-side metallized layer 2a provided around the peripheral edge of the board 2 for jointing with the solder 7. The layer 6a has a width larger than that of the layer 2a, and a board-side joint surface 7b of the solder 7 for jointing with the layer 2a is arranged at a location, corresponding to the inner region of the surface 6b of the member 6 in the board 2, whereby the formation of cracks in the board 2 can be prevented.

9. 发明专利

JP2001015633A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001015633A
公开(公告)日：2001-01-19
申请号：JP18307799
申请日：1999-06-29
申请人： HITACHI LTD
发明人： KIKUCHI HIROSHI , YOSHIDA IKUO , SATO TOSHIHIKO , SUMI YOSHIYUKI
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To elongate the lifetime of connections between electrode pads of a wiring substrate and electrode pads of a semiconductor chip by constituting the wiring substrate having electrode pads of a second group electrically connected to electrode pads of a first group with a main substrate material of a flexible film. SOLUTION: A wiring substrate 1 has a squared planar shape, and is mainly constituted by a flexible film 2 of polyimide-family insulator resin. A plurality of wires 3 are formed on a main surface 1A of the wiring substrate 1, and for the wires 3, electrode pads 3A of a first group are respectively formed. Also, a plurality of wires 5 are formed on the other main surface 1B of the wiring substrate 1, and for the wires 5, electrode pads 5A of a second group are respectively formed. With such arrangements, a semiconductor chip 10 is mounted on the main surface 1A side of the wiring substrate 1, and a plurality of conductive bumps 14 are arranged as external terminals on the other main surface 1B side of the wiring substrate 1.

10. 发明专利

JPH10107173A SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JPH10107173A
公开(公告)日：1998-04-24
申请号：JP26160996
申请日：1996-10-02
申请人： HITACHI LTD
发明人： DOI HIROAKI , KOUNO MASAYA , YASUKAWA AKIO , SATO TOSHIHIKO
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To prevent a solder connection defect while the height of a solder bump is being maintained by a method wherein an elastic body is installed at the semiconductor package and the position of the elastic body in a deformed state is held by a spacer which is softened at the temperature of the melting point of higher of a solder electrode. SOLUTION: Solder electrodes 4 are connected to the rear surface of a ceramic package 3 in which a semiconductor element 1 is connected by solder pieces 2, a stainless steel plate 5 as an elastic body is brazed to the surface of the ceramic package 3, and the stainless steel plate 5 is elastically deformed upward by a high-melting-point solder piece 6 which is fixed and bonded to the surface of the ceramic package 3. Thereby, the gap at a mounting structure between the ceramic package 3 and the semiconductor element 1 is held properly, a soldering defect is not generated, a strain which is generated in a connecting solder piece owing to a substrate bend generated in a handling operation of owing to a temperature change is reduced, and it is possible to prevent the connecting solder piece from being broken down.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式