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21. 发明专利

JPH06150023A MICROCOMPUTER AND SYSTEM THEREOF 失效
公开(公告)号：JPH06150023A
公开(公告)日：1994-05-31
申请号：JP32259892
申请日：1992-11-06
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , FUKADA KAORU , WATABE MITSURU , NOGUCHI YOSHIKI , MATSUBARA KIYOSHI , MOCHIZUKI ISAMU , SUZUKAWA KAZUFUMI , MASUMURA SHIGEKI , AKAO YASUSHI , SAKAKIBARA EIJI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78
摘要： PURPOSE:To flexibly deal with required system construction by adopting an interface for a dynamic RAM and an interface for a memory such as a static RAM and a peripheral circuit to the microcomputer. CONSTITUTION:This microcomputer is provided with strobe signal output terminals CASH, CASL and RAS for the dynamic RAM and chip select signal output terminals CSO-CS6 for outputting chip select signals parallelly to respective outputs. Then, an address output terminal can output non-multiplexed address signals or address signals multiplexed as needed, and the input/output terminal of data is provided for selectively outputting the address signals so as to cope with the multibus system interface. Thus, the interface for the dynamic RAM and the interface for the memory such as the static RAM and the other peripheral circuit are adopted to the microcomputer.

22. 发明专利

JPH05197546A MICROCOMPUTER AND DIVIDING CIRCUIT 失效
公开(公告)号：JPH05197546A
公开(公告)日：1993-08-06
申请号：JP15452592
申请日：1992-05-21
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： PURPOSE:To decrease program capacity or improve the utilization efficiency of a program memory by employing a fixed length instruction format which is smaller in the number of bits than the maximum length of data words supplied to an instruction executing means. CONSTITUTION:The microcomputer has RISC(reduced instruction set type computer) type architecture and has the fixed length instruction format. When data and instructions are transferred, a bus, e.g. an internal data bus IDB is of 32-bit constitution, but the instructions are in 16-bit fixed length instruction format. Then 16-bit instruction buffers (instruction queue) IRH and IRL store the instructions, one by one, and the instructions are loaded respectively in a single instruction fetch cycle. The instructions are transferred in 32-bit units through the internal data bus IDB and then loaded in an instruction register IR1 through a multiplexer MPX. Then the 16-bit instruction register IR1 holds the instructions present in an instruction decoding stage.

23. 发明专利

JPH04372019A PIPELINE CONTROLLER AND MICROCOMPUTER 失效
公开(公告)号：JPH04372019A
公开(公告)日：1992-12-25
申请号：JP15009991
申请日：1991-06-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MASUMURA SHIGEKI , NAKAMURA HIDEO , NOGUCHI YOSHIKI , KAWASAKI SHUNPEI
IPC分类号： G06F9/38
摘要： PURPOSE:To be a variable control content according to a processing content by controlling the execution of the pipeline at every execution step using a software program independent of the processing content that is executed by an electronic circuit. CONSTITUTION:An instruction for the execution of a processing is converted into the first address of a control ROM 104 by a mapping ROM 102. The corresponding microinstruction inputted to the control ROM 104 is read to a microinstruction register 105. The control instruction of a pipeline control field 107 is inputted to a sequence control part 108 and a pipeline control part 109. The control part 108 generates data necessary for the next address control, address selection control, and address conversion control and a control signal 122, supplies them to a selector 10 and the ROM 102, and controls them. The control part 109 generates the pipeline control signal 121 and performs the integrated control of a timing control means necessary for the pipeline execution and the control of the data process.

24. 发明专利

JPS6468829A ARITHMETIC UNIT 失效
公开(公告)号：JPS6468829A
公开(公告)日：1989-03-14
申请号：JP22689587
申请日：1987-09-10
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MIURA MASAHARU , KAWASAKI SHUNPEI
IPC分类号： G06F7/00 , G06F7/57 , G06F7/76 , G06F9/308 , G06F9/315 , G06F9/318
摘要： PURPOSE:To quickly operate data whose structure has first and second information fields, by providing a preserving means which preserves information in a prescribed second information field of input data as arithmetic result output data. CONSTITUTION:A tag field TFa of one input data A0-A15 is masked with logical '0' in case of OR, exclusive OR, addition, or the like and the tag field TFa of one input data A0-A15 is masked with logical '1' in case of AND, subtraction, or the like to execute the arithmetic logic operation between a pair of input data. When carry is transmitted from lower digits to upper four-bit arithmetic results D15-D12 at this time, the result of arithmetic logic operation between data fields DFa and DFb is included in arithmetic results D0-D15 and information B15-B12 in tag fields TFb of input data B0-B15 are preserved as they are. Thus, the arithmetic logic operation of data with tags is quickly executed in one step.

25. 发明专利

JPS63163634A INSTRUCTION FETCH SYSTEM 失效
公开(公告)号：JPS63163634A
公开(公告)日：1988-07-07
申请号：JP30840886
申请日：1986-12-26
申请人： HITACHI LTD
发明人： SAKOTA KOUSUKE , KAWASAKI SHUNPEI , NAKAO KAZUO
IPC分类号： G06F9/38
摘要： PURPOSE:To improve feasible performance, by always placing an instruction to be issued at the next step at the leading position of a specific register when the instructions of one byte or two or more bytes are mixed. CONSTITUTION:A data, at the leading position of which the instruction to be taken out at the next step is included, is always inputted in a first register 3, and when the instruction is requested, the instruction of required number of bytes is taken out from the leading position of the first register 3. The data is complemented immediately from a second register 11 to the first register 3 by a shift operation. When the second register 11 becomes vacant, the data is read out from a memory device and is complemented. When the instructions of one byte or two or more bytes are mixed, since the instruction to be taken out at the next step is present at the leading position of the specific register, and it is possible to take out the required number of bytes by issuing designation by a microinstruction, it is possible to eliminate overhead for the taking out of the instruction and to accelerate execution.

26. 发明专利

JPS62259139A MICROPROGRAM CONTROLLER 失效
公开(公告)号：JPS62259139A
公开(公告)日：1987-11-11
申请号：JP10349586
申请日：1986-05-06
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SAKOTA KOUSUKE , KAWASAKI SHUNPEI , NOJIRI TORU , TAKAHASHI FUMIHIRO
IPC分类号： G06F9/26 , G06F9/22
摘要： PURPOSE:To attain the highly effective application of a memory by storing the logic operation results on two data in a qualification register to obtain the OR of the contents of the qualification register and an address designating filed and using said OR as the next microinstruction. CONSTITUTION:The contents of a register 12 are outputted to a data bus 10 with the constant 101 of a constant designating part 5 outputted to a data bus 9 respectively by the 1st microinstruction and with the designation of a control signal generating part 4. While the part 4 designates a fact that the value obtained by an arithmetic designating part 6 with the AND of values of both buses 9 and 10 is outputted to a correction register 14 after control of selection circuits 31 and 32. Thus the data 102 is set to the register 14. For instance, a branch address 103 is designated in case both of two 'd' are equal to 0 when branching is carried out in four directions by the reference data 100 via an address designating part of the 2nd microinstruction. Then the microinstruction set at the address shown by 104 is carried out when the 2nd microinstruction is carried out. In other words, the branching is possible in four directions according to the value of 'd'.

27. 发明专利

JPS61237135A INSTRUCTION PRE-FETCHING SYSTEM 失效
公开(公告)号：JPS61237135A
公开(公告)日：1986-10-22
申请号：JP7835385
申请日：1985-04-15
申请人： HITACHI LTD
发明人： IWASAKI KAZUHIKO , KAWASAKI SHUNPEI , HAGIWARA YOSHIMUNE
IPC分类号： G06F15/16 , G06F9/38
摘要： PURPOSE:To shorten an idle state of an MPU by executing an address calculation of the second call processor instruction, a fetch of an operand data, etc., by the MPU, when a Co-Processor is executing the first call processor instruction. CONSTITUTION:When a Co-Processor executes the first Co-Processing instruction, and reaches a pre-fetch means, an MPU executes a pre-fetch of the second Co-Processor instruction. Also, the MPU executes a fetch of the second Co- Processor instruction which follows the first Co-Processing instruction, decoding, an address calculation of an operand, and a fetch of an operand data. When an end signal from the Co-Processor is received, the MPU transfers a data required for executing the instruction, to the Co-Processor.

28. 发明专利

JP2000029692A CENTRAL PROCESSOR 失效
公开(公告)号：JP2000029692A
公开(公告)日：2000-01-28
申请号：JP13977299
申请日：1999-05-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/355 , G06F9/34
摘要： PROBLEM TO BE SOLVED: To decrease program capacity or increase the efficiency of a program memory and to reduce the system cost by adopting a fixed-length instruction format whose bit number is less than the maximum data word length supplied to an instruction executing means. SOLUTION: An instruction register IR1 holds an instruction present at an instruction decoding means. The decoding results of a source register decoder SRD and a destination register decoder DRD are used to specify which of general register R0H, R0L to R15H, and R15L included in an execution part EXEC is selected. With a data transfer instruction, data stored in the address obtained by adding a value of displacement and the value of an address stored in a program counter are transferred to one of registers. In this case, the fixed-length instruction format whose bit number is less than the maximum data word length supplied to the instruction execution means is adopted.

29. 发明专利

JP2540794B2 失效
公开(公告)号：JP2540794B2
公开(公告)日：1996-10-09
申请号：JP4112085
申请日：1985-03-04
申请人： HITACHI LTD
发明人： SHIMA KAZUMASA , KAWASAKI SHUNPEI , KUBO TAKASHIGE
IPC分类号： H01L21/82 , H03K19/177
摘要： A programmable logic array circuit which assumes terms which are not implicants to be DON'T CARE terms, and which produces a logic function having decreased number of product terms; and which has a logic function which eliminates the terms that have been regarded to be DON'T CARE terms.

30. 发明专利

JPH05216658A METHOD AND DEVICE FOR PROCESSING WORD COMPARISON INSTRUCTION AND METHOD AND DEVICE FOR PROCESSING CHARACTER STRING COMPARISON INSTRUCTION 失效
公开(公告)号：JPH05216658A
公开(公告)日：1993-08-27
申请号：JP2082892
申请日：1992-02-06
申请人： HITACHI LTD , HITACHI KEIYO ENG
发明人： YAMADA KOSHI , UMINAGA MASAHIRO , HIUGA NOBUO , KAWASAKI SHUNPEI , AKAO YASUSHI
IPC分类号： G06F7/04 , G06F9/305 , G06F17/16
摘要： PURPOSE:To speed up a character string comparing process like the strcmp function of, for example, the C language by comparing two character strings which have optional length, word by word. CONSTITUTION:The methods and device are equipped with a large/small comparator 230 which compares 1st word data which are the contents of a 1st register 201 with 2nd word data which are the contents of a 2nd register 202, a terminating character detector 220 which inspects whether or not the 2nd word data contains a terminating character, and an encoder 240 which outputs an output value for discriminating a case wherein the 1st word data is larger than the 2nd word data, a case wherein the 1st word data is smaller than the 2nd word data, and a case wherein the 1st word data is equal to the 2nd word data and the character string terminating character is present in one of the word data, and a case wherein the 1st word data is equal to the 2nd word data and the character string terminating character is present in neither of the word data, to a 3rd register 203 according to the outputs of the large/small comparator 230 and terminating character detector 220.

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