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    • 22. 发明授权
    • Ferroelectric memory cell array and method of storing data using the same
    • 铁电存储单元阵列及使用其存储数据的方法
    • US06636435B2
    • 2003-10-21
    • US10032987
    • 2001-12-27
    • Yil Suk YangTae Moon RohJong Dae KimByoung Gon Yu
    • Yil Suk YangTae Moon RohJong Dae KimByoung Gon Yu
    • G11C1122
    • G11C11/22
    • The present invention relates to a ferroelectric memory cell array formed of a single transistor, and method of storing data using the same. The ferroelectric memory cell array includes a plurality of word lines connected to gates of the memory cells located at respective rows, a plurality of bit lines connected to drains of the memory cells located at respective columns, a common source line commonly connecting sources of the memory cells, and a plurality of well lines each connected to wells in which the memory cells are each formed, wherein a bias voltage of an unit pulse shape is applied to a gate of a selected memory cell and a bias voltage of a pulse shape is applied to a well line. Therefore, the present invention allows a random access without a disturbance since data can be written by means of the polarity characteristic of the ferroelectric.
    • 本发明涉及由单个晶体管形成的铁电存储单元阵列,以及使用该晶体管存储数据的方法。 铁电存储单元阵列包括连接到位于各行的存储单元的栅极的多条字线,连接到位于相应列的存储单元的漏极的多个位线,通常连接存储器的源极的公共源极线 单元和多个井管线,每个阱管线连接到其中形成有存储单元的阱,其中单位脉冲形状的偏置电压被施加到所选存储单元的栅极并施加脉冲形状的偏置电压 到一条井线 因此,本发明允许无障碍地随机存取,因为可以通过铁电体的极性特性写入数据。
    • 27. 发明授权
    • Reconfigurable arithmetic unit and high-efficiency processor having the same
    • 可重构算术单元和具有相同功能的高效处理器
    • US08150903B2
    • 2012-04-03
    • US12136107
    • 2008-06-10
    • Yil Suk YangJung Hee SukChun Gi LyuhTae Moon RohJong Dae Kim
    • Yil Suk YangJung Hee SukChun Gi LyuhTae Moon RohJong Dae Kim
    • G06F7/57
    • G06F7/57G06F7/5324G06F7/5338
    • Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.
    • 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器,用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数,用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品,用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器(MUX),用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器(CPA),以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作,从而可以增加整个硬件的使用程度。
    • 29. 发明授权
    • Highly energy-efficient processor employing dynamic voltage scaling
    • 采用动态电压调节的高能效处理器
    • US07805620B2
    • 2010-09-28
    • US11520177
    • 2006-09-13
    • Yil Suk YangJong Dae KimSoon Il YeoChun Gi Lyuh
    • Yil Suk YangJong Dae KimSoon Il YeoChun Gi Lyuh
    • G06F1/00
    • G06F1/3203G06F1/3287G06F1/3293G06F1/3296Y02D10/122Y02D10/171Y02D10/172Y02D50/20
    • Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.
    • 提供了一种高能效的处理器架构。 该架构采用2级动态电压调节(DVS)和睡眠模式以实现高能效,通过指令动态控制电源电压和嵌入式处理器的激活,从而可以在降低功耗的同时防止性能下降。 采用该处理器架构的高能效处理器包括:功能单元块,用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器,用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器,用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。