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1. 发明授权

US06887772B2 Structures of high voltage device and low voltage device, and method of manufacturing the same 失效
标题翻译：高压器件和低压器件的结构及其制造方法
公开(公告)号：US06887772B2
公开(公告)日：2005-05-03
申请号：US10721970
申请日：2003-11-24
申请人： Dae Woo Lee , Tae Moon Roh , Yil Suk Yang , Il Yong Park , Byoung Gon Yu , Jong Dae Kim
发明人： Dae Woo Lee , Tae Moon Roh , Yil Suk Yang , Il Yong Park , Byoung Gon Yu , Jong Dae Kim
IPC分类号： H05B33/00 , H01L21/8234 , H01L27/088 , H01L27/12 , H01L21/20 , H01L21/76 , H01L21/8238
CPC分类号： H01L21/823462 , H01L27/088 , H01L27/1203
摘要： The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.
摘要翻译：本发明涉及形成在SOI衬底上的高电压器件和低电压器件的结构及其制造方法，其特征在于SOI衬底中硅器件区域的低电压器件区域较高比高压器件区域逐步，并且形成高压器件的硅器件区域的厚度等于低压器件中的源极和漏极的杂质的结深度。因此，SOI衬底中的硅器件区域被分成高压区域和低电压区域，并且通过氧化生长方法在其间形成步骤，使得可以制造具有低结电容的高电压器件，并且低电压与传统CMOS工艺兼容的器件和器件特性也可以同时进行。

2. 发明授权

US07403178B2 Sources driver circuit for active matrix electroluminescent display and driving method thereof 有权
标题翻译：用于有源矩阵电致发光显示器的源极驱动电路及其驱动方法
公开(公告)号：US07403178B2
公开(公告)日：2008-07-22
申请号：US10817838
申请日：2004-04-06
申请人： Yil Suk Yang , Jong Dae Kim , Dae Woo Lee , Tae Moon Roh , Il Yong Park , Sung Ku Kwon , Byoung Gon Yu
发明人： Yil Suk Yang , Jong Dae Kim , Dae Woo Lee , Tae Moon Roh , Il Yong Park , Sung Ku Kwon , Byoung Gon Yu
IPC分类号： G09G3/30 , G09G3/20 , G09G3/22
CPC分类号： G09G3/30 , G09G2310/027 , G09G2320/0276
摘要： Provided is a source driver circuit for an active matrix electroluminescent (EL) display including a digital-to-analog converter/ramp circuit for converting a digital signal into an analog signal, and generating a ramp signal in this process, simultaneously, whereby high degree of integration would be possible since a conventional complicated circuit is not required and gray scale with the high characteristic can be implanted, regardless of a change of a temperature or a threshold voltage.
摘要翻译：提供了一种用于有源矩阵电致发光（EL）显示器的源极驱动电路，其包括用于将数字信号转换为模拟信号的数模转换器/斜坡电路，并且在该过程中同时产生斜坡信号，由此高度的集成是可能的，因为不需要常规的复杂电路，而不管温度或阈值电压的变化，都可以植入具有高特性的灰度级。

3. 发明授权

US06636435B2 Ferroelectric memory cell array and method of storing data using the same 有权
标题翻译：铁电存储单元阵列及使用其存储数据的方法
公开(公告)号：US06636435B2
公开(公告)日：2003-10-21
申请号：US10032987
申请日：2001-12-27
申请人： Yil Suk Yang , Tae Moon Roh , Jong Dae Kim , Byoung Gon Yu
发明人： Yil Suk Yang , Tae Moon Roh , Jong Dae Kim , Byoung Gon Yu
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： The present invention relates to a ferroelectric memory cell array formed of a single transistor, and method of storing data using the same. The ferroelectric memory cell array includes a plurality of word lines connected to gates of the memory cells located at respective rows, a plurality of bit lines connected to drains of the memory cells located at respective columns, a common source line commonly connecting sources of the memory cells, and a plurality of well lines each connected to wells in which the memory cells are each formed, wherein a bias voltage of an unit pulse shape is applied to a gate of a selected memory cell and a bias voltage of a pulse shape is applied to a well line. Therefore, the present invention allows a random access without a disturbance since data can be written by means of the polarity characteristic of the ferroelectric.
摘要翻译：本发明涉及由单个晶体管形成的铁电存储单元阵列，以及使用该晶体管存储数据的方法。铁电存储单元阵列包括连接到位于各行的存储单元的栅极的多条字线，连接到位于相应列的存储单元的漏极的多个位线，通常连接存储器的源极的公共源极线单元和多个井管线，每个阱管线连接到其中形成有存储单元的阱，其中单位脉冲形状的偏置电压被施加到所选存储单元的栅极并施加脉冲形状的偏置电压到一条井线因此，本发明允许无障碍地随机存取，因为可以通过铁电体的极性特性写入数据。

4. 发明授权

US07335945B2 Multi-gate MOS transistor and method of manufacturing the same 有权
标题翻译：多栅极MOS晶体管及其制造方法
公开(公告)号：US07335945B2
公开(公告)日：2008-02-26
申请号：US11012695
申请日：2004-12-16
申请人： Dae Woo Lee , Tae Moon Roh , Sung Ku Kwon , Il Yong Park , Yil Suk Yang , Byoung Gon Yu , Jong Dae Kim
发明人： Dae Woo Lee , Tae Moon Roh , Sung Ku Kwon , Il Yong Park , Yil Suk Yang , Byoung Gon Yu , Jong Dae Kim
IPC分类号： H01L29/78 , H01L21/8234
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66795 , H01L29/78645
摘要： Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.
摘要翻译：提供一种多栅极MOS晶体管及其制造方法。垂直堆叠在硅绝缘体（SOI）基板上的两个硅散热片，上硅片的四个侧表面和下硅片的三个侧表面用作通道。因此，通道宽度增加，从而提高了器件的电流驱动能力，并且可以通过工艺的优化和稳定性来制造高性能纳米级半导体IC和高度集成的存储器IC。

5. 发明授权

US06759714B2 Semiconductor device having heat release structure using SOI substrate and fabrication method thereof 有权
标题翻译：具有使用SOI衬底的放热结构的半导体器件及其制造方法
公开(公告)号：US06759714B2
公开(公告)日：2004-07-06
申请号：US10322232
申请日：2002-12-17
申请人： Sang Gi Kim , Dae Woo Lee , Tae Moon Roh , Yil Suk Yang , II-Young Park , Byoung-Gon Yu , Jong Dae Kim
发明人： Sang Gi Kim , Dae Woo Lee , Tae Moon Roh , Yil Suk Yang , II-Young Park , Byoung-Gon Yu , Jong Dae Kim
IPC分类号： H01L2972
CPC分类号： H01L21/76289 , H01L21/84 , H01L23/367 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.
摘要翻译：提供半导体制造技术; 更具体地说，涉及具有使用绝缘体上硅（SOI）衬底的散热结构的半导体器件，以及制造半导体器件的方法。本研究的装置和方法提供了具有高散热结构和高放热结构的半导体器件及其制造方法。在研究中，通过在绝缘体上硅（SOI）衬底上形成集成电路，快速地通过隧道区域在衬底外部释放集成电路中产生的热和高频噪声，除去埋入集成电路下的绝缘层形成隧道区。当在隧道区域的上部和下部的表面上形成不均匀时，或者当具有优良导热性的空气或其它气体流入隧道区域时，可以进一步提高散热效率。

6. 发明授权

US08150903B2 Reconfigurable arithmetic unit and high-efficiency processor having the same 有权
标题翻译：可重构算术单元和具有相同功能的高效处理器
公开(公告)号：US08150903B2
公开(公告)日：2012-04-03
申请号：US12136107
申请日：2008-06-10
申请人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
发明人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F7/57
CPC分类号： G06F7/57 , G06F7/5324 , G06F7/5338
摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.
摘要翻译：提供了一种可重构运算单元和具有该可重配置运算单元的处理器。可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

7. 发明授权

US07576582B2 Low-power clock gating circuit 有权
标题翻译：低功耗时钟门控电路
公开(公告)号：US07576582B2
公开(公告)日：2009-08-18
申请号：US11945387
申请日：2007-11-27
申请人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
发明人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.
摘要翻译：提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用单阈值电压。

8. 发明申请

US20080291198A1 METHOD OF PERFORMING 3D GRAPHICS GEOMETRIC TRANSFORMATION USING PARALLEL PROCESSOR 审中-公开
标题翻译：使用并行处理器执行3D图形几何变换的方法
公开(公告)号：US20080291198A1
公开(公告)日：2008-11-27
申请号：US12100707
申请日：2008-04-10
申请人： Ik Jae Chun , Jung Hee Suk , Yil Suk Yang , Dae Woo Lee , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Jung Woo Lee
发明人： Ik Jae Chun , Jung Hee Suk , Yil Suk Yang , Dae Woo Lee , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Jung Woo Lee
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： Provided is a method of performing three-dimensional (3D) graphics geometric transformation using a parallel processor having a plurality of Processing Elements (PEs). The method includes performing model/view transformation and projection transformation on a first group of vertex vectors using the parallel processor; calculating a value used for quaternion correction of the first group of vertex vectors using a general-use processor, and simultaneously performing model/view transformation and projection transformation on a second group of vertex vectors; performing quaternion correction and screen mapping on the first group of vertex vectors, and simultaneously calculating a value used for quaternion correction of the second group of vertex vectors using the general-use processor; and performing quaternion correction and screen mapping on the second group of vertex vectors.
摘要翻译：提供了一种使用具有多个处理元件（PE）的并行处理器执行三维（3D）图形几何变换的方法。该方法包括使用并行处理器对第一组顶点向量执行模型/视图变换和投影变换; 使用通用处理器计算用于第一组顶点矢量的四元数校正的值，并且同时对第二组顶点矢量执行模型/视图变换和投影变换; 对所述第一组顶点向量进行四元数校正和画面映射，并且使用所述通用处理器同时计算用于所述第二组顶点向量的四元数校正的值; 并对第二组顶点向量执行四元数校正和屏幕映射。

9. 发明申请

US20080133879A1 SIMD parallel processor with SIMD/SISD/row/column operation modes 审中-公开
标题翻译： SIMD并行处理器采用SIMD / SISD /行/列操作模式
公开(公告)号：US20080133879A1
公开(公告)日：2008-06-05
申请号：US11906381
申请日：2007-10-01
申请人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim , Chun Gi Lyuh
发明人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim , Chun Gi Lyuh
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/30098 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/30181 , G06F9/30189
摘要： Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required for any one of SIMD, single instruction single data (SISD), row, and column operations in response to an instruction. Since each of the SIMD, SISD, row, and column operations can be effectively performed according to the type of application, the SIMD parallel processor has excellent utility, efficiency, and flexibility.
摘要翻译：提供了包括彼此连接的多个处理单元的单指令多数据（SIMD）并行处理器。每个处理单元包括：指令寄存器; 指令解码器; 寄存器文件选择电路; 并注册文件。 SIMD并行处理器可以选择性地控制响应于指令的SIMD，单指令单数据（SISD），行和列操作中的任何一个所需的寄存器文件的数据。由于可以根据应用类型有效地执行SIMD，SISD，行和列操作，所以SIMD并行处理器具有优异的效用，效率和灵活性。

10. 发明授权

US06774697B2 Input and output port circuit 有权
标题翻译：输入输出端口电路
公开(公告)号：US06774697B2
公开(公告)日：2004-08-10
申请号：US10325929
申请日：2002-12-23
申请人： Yil Suk Yang , Jong Dae Kim , Tae Moon Roh , Jin Gun Koo , Dae Woo Lee , Sang Gi Kim , Il Yong Park
发明人： Yil Suk Yang , Jong Dae Kim , Tae Moon Roh , Jin Gun Koo , Dae Woo Lee , Sang Gi Kim , Il Yong Park
IPC分类号： H03L500
CPC分类号： H03K19/0016
摘要： The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.
摘要翻译：本发明涉及输入和输出端口电路。输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及输出控制电路的输出。高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。因此，可以节省功耗。

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