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21. 发明申请

US20100262813A1 Detecting and Handling Short Forward Branch Conversion Candidates 审中-公开
标题翻译：检测和处理短期分支转换候选人
公开(公告)号：US20100262813A1
公开(公告)日：2010-10-14
申请号：US12423608
申请日：2009-04-14
申请人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F8/433 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3844 , G06F9/3846 , G06F9/3855
摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
摘要翻译：在处理器中提供用于检测和处理短前进分支转换候选的机制。机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。

22. 发明授权

US08261276B2 Power-efficient thread priority enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US08261276B2
公开(公告)日：2012-09-04
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46 , G06F9/00 , G06F13/28 , G06F1/32
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

23. 发明授权

US07826399B2 Structure for preventing starvation in a slotted ring data communications network 失效
标题翻译：用于在时隙环数据通信网络中防止饥饿的结构
公开(公告)号：US07826399B2
公开(公告)日：2010-11-02
申请号：US12042612
申请日：2008-03-05
申请人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
发明人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
IPC分类号： H04L12/43
CPC分类号： H04L12/4035 , H04L12/66
摘要： A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
摘要翻译：为时隙环网提供了一种设计结构，其中节点可以用任何未预留的时隙发送不可再生的时隙预留。该预约限制其他节点在时隙中发送新的分组。当插槽返回环到保留节点时，插槽将可用。优选地，响应于预留节点中的饥饿状况做出预约，其可以以各种方式中的任一种来检测。在可选增强中，预留识别预留节点，并且如果新分组将在保留节点处或之前到达其目的地，则环上的另一个节点可以自由地在保留时隙中发送新分组，并且因此不会干扰预订。

24. 发明授权

US07716264B2 Method and apparatus for performing alignment shifting in a floating-point unit 有权
标题翻译：用于在浮点单元中执行对准移位的方法和装置
公开(公告)号：US07716264B2
公开(公告)日：2010-05-11
申请号：US11205987
申请日：2005-08-16
申请人： Sherman M. Dance , Jeffrey R. Summers , Shivakumar Swaminathan
发明人： Sherman M. Dance , Jeffrey R. Summers , Shivakumar Swaminathan
IPC分类号： G06F15/00
CPC分类号： G06F5/01
摘要： An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount under a double-precision mode and two shift amounts under a single-precision mode. The first level shifters can concurrently receive two double-precision mantissas under the double-precision mode or two single-precision mantissas under the single-precision mode. The first level of shifts performs small shifts concurrently on the two double-precision mantissas according to the single shift amount, or on the two single-precision mantissas according to the two shift amounts. The second level shifters performs large shifts on outputs from the first level shifters to generate one double-precision floating-point result or two single-precision floating-point results.
摘要翻译：公开了一种用于在浮点单元中进行对准移位的装置。对准移位器包括移位量计算器，一组第一电平移位器和一组第二电平移位器。移位量计算器在双精度模式下产生一个移位量，并在单精度模式下产生两个移位量。第一级移位器可以在双精度模式下同时接收两个双精度尾数，或者在单精度模式下同时接收两个单精度尾数。第一级别的换档根据单位移量在两个双精度尾数上同时执行小移动，或者根据两个移位量在两个单精度尾数上同时进行。第二电平移位器对来自第一电平移位器的输出执行大的移位，以产生一个双精度浮点运算或两个单精度浮点运算结果。

25. 发明申请

US20080130667A1 DISTRIBUTED ARBITRATION MECHANISM FOR RING NETWORKS 审中-公开
标题翻译：用于环网的分布式仲裁机制
公开(公告)号：US20080130667A1
公开(公告)日：2008-06-05
申请号：US11564863
申请日：2006-11-30
申请人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
发明人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
IPC分类号： H04L12/66
CPC分类号： H04L12/66
摘要： A system for employing a scalable distributed arbitration scheme, including: a plurality of stations interconnected via a ring topology for transferring data between the plurality of stations; and a bus coupling the plurality of stations in the ring topology; wherein each of the plurality of stations on the topology ring is permitted to independently make a decision when to load their data on the topology ring by evaluating a set of inputs.
摘要翻译：一种采用可扩展分布仲裁方案的系统，包括：通过环形拓扑互连的多个站，用于在多个站之间传送数据; 以及耦合所述环形拓扑中的所述多个站的总线; 其中允许拓扑环上的多个站中的每一个通过评估一组输入来独立地决定何时将其数据加载到拓扑环上。

26. 发明授权

US08127115B2 Group formation with multiple taken branches per group 失效
标题翻译：每组多组分组成组
公开(公告)号：US08127115B2
公开(公告)日：2012-02-28
申请号：US12417798
申请日：2009-04-03
申请人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James Albert Van Norstrand, Jr.
发明人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James Albert Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853
摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.
摘要翻译：公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。

27. 发明申请

US20070297441A1 Method and Apparatus for Preventing Starvation in a Slotted Ring Data Communications Network 失效
标题翻译：用于在开槽环数据通信网络中预防饥饿的方法和装置
公开(公告)号：US20070297441A1
公开(公告)日：2007-12-27
申请号：US11426746
申请日：2006-06-27
申请人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
发明人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
IPC分类号： H04L12/43
CPC分类号： H04L12/4035 , H04L12/423
摘要： In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
摘要翻译：在时隙环网络中，节点可以用任何未预留的时隙发送不可更新的时隙预留。该预约限制其他节点在时隙中发送新的分组。当插槽返回环到保留节点时，插槽将可用。优选地，响应于预留节点中的饥饿状况做出预约，其可以以各种方式中的任一种来检测。在可选增强中，预留识别预留节点，并且如果新分组将在保留节点处或之前到达其目的地，则环上的另一个节点可以自由地在保留时隙中发送新分组，并且因此不会干扰预订。

28. 发明申请

US20100257340A1 System and Method for Group Formation with Multiple Taken Branches Per Group 失效
标题翻译：每组多组分组形成的系统和方法
公开(公告)号：US20100257340A1
公开(公告)日：2010-10-07
申请号：US12417798
申请日：2009-04-03
申请人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James A. Van Norstrand, JR.
发明人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James A. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853
摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.
摘要翻译：公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。

29. 发明申请

US20090249349A1 Power-Efficient Thread Priority Enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US20090249349A1
公开(公告)日：2009-10-01
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

30. 发明授权

US07467366B2 Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components 失效
标题翻译：用于生成用于识别耦合在组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法
公开(公告)号：US07467366B2
公开(公告)日：2008-12-16
申请号：US11535203
申请日：2006-09-26
申请人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
发明人： John B. Blankenship , Kevin N. Magill , Jeffrey R. Summers , Anup Wadia
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.
摘要翻译：提供了一种用于生成用于识别耦合在第一和第二组件之间的硬件设备中的关键定时路径的定时路径软件监视器的方法。该方法包括生成与硬件设备相关联的静态定时报告。静态定时报告具有与耦合到硬件设备的线路相关联的硬件设备和线名称。该方法还包括基于静态定时报告自动生成定时路径软件监视器，静态定时报告在第一时钟周期监视与线名称相关联的二进制值，以及在第一时钟周期之后的第二时钟周期期间与线名相关联的二进制值的转变时钟周期。定时路径软件监视器指示当在第二时钟周期期间发生由第二分量接收的二进制值之一的转换时，识别关键定时路径。

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