专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100257340A1 System and Method for Group Formation with Multiple Taken Branches Per Group 失效
标题翻译：每组多组分组形成的系统和方法
公开(公告)号：US20100257340A1
公开(公告)日：2010-10-07
申请号：US12417798
申请日：2009-04-03
申请人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James A. Van Norstrand, JR.
发明人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James A. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853
摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.
摘要翻译：公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。

2. 发明授权

US08127115B2 Group formation with multiple taken branches per group 失效
标题翻译：每组多组分组成组
公开(公告)号：US08127115B2
公开(公告)日：2012-02-28
申请号：US12417798
申请日：2009-04-03
申请人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James Albert Van Norstrand, Jr.
发明人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James Albert Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853
摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.
摘要翻译：公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式