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21. 发明授权

US5614815A Constant voltage supplying circuit 失效
标题翻译：恒压供电电路
公开(公告)号：US5614815A
公开(公告)日：1997-03-25
申请号：US401272
申请日：1995-03-09
申请人： Seiji Yamagata , Shinya Udo , Fumitaka Asami
发明人： Seiji Yamagata , Shinya Udo , Fumitaka Asami
IPC分类号： G05F3/24 , G05F3/16
CPC分类号： G05F3/247
摘要： A constant voltage supplying circuit is disposed between a voltage output terminal of a voltage generation circuit for outputting a voltage having the same polarity as that of a reference voltage, which can be arbitrarily set, and having a greater absolute value than the reference voltage, and a load. This constant voltage supplying circuit includes a first field effect transistor a gate of which is connected to its drain, and to a source of which the reference voltage is supplied, and a second field effect transistor which has the same conductivity type as the first field effect transistor, a gate of which is connected to the drain of the first field effect transistor, a source of which is connected to the voltage output terminal of the voltage generation circuit, and a drain of which is connected to the ground. According to the circuit constitution, the output voltage of the voltage generation circuit can be stabilized to a desired voltage value (the same voltage value as the reference voltage). Even when the constant voltage supplying circuit is fabricated in an integrated circuit, it does not invite the increase of the production process, and thus can limit the increase of the cost of production.
摘要翻译：恒压供给电路设置在电压产生电路的电压输出端子之间，用于输出具有与参考电压相同极性的电压，该参考电压可以任意设置，并且具有比参考电压更大的绝对值;以及负载。该恒压供给电路包括第一场效应晶体管，其栅极连接到其漏极，并连接到提供参考电压的源极;以及第二场效应晶体管，其具有与第一场效应相同的导电类型晶体管，其栅极连接到第一场效应晶体管的漏极，源极连接到电压产生电路的电压输出端，其漏极连接到地。根据电路结构，电压产生电路的输出电压可以稳定到期望的电压值（与参考电压相同的电压值）。即使在集成电路中制造恒压供给电路的情况下，也不会引起生产过程的增加，因此可以限制生产成本的增加。

22. 发明授权

US5596294A Synchronizing circuit for dividing a frequency of a clock signal supplied from an external device into a plurality of internal clock signals 失效
标题翻译：用于将从外部设备提供的时钟信号的频率分成多个内部时钟信号的同步电路
公开(公告)号：US5596294A
公开(公告)日：1997-01-21
申请号：US492311
申请日：1995-06-19
申请人： Noriko Kadomaru , Fumitaka Asami
发明人： Noriko Kadomaru , Fumitaka Asami
IPC分类号： H04N5/06 , G06F1/06 , G06F1/12 , H03K5/00 , H03L7/00 , H03K1/04
CPC分类号： H03K5/00006 , G06F1/06 , G06F1/12 , H03L7/00
摘要： A synchronizing circuit has a first signal generating unit for dividing a control signal to obtain a first signal having a first frequency, a second signal generating unit for dividing the control signal to obtain a second signal having a second frequency, a third signal generating unit for dividing the control signal to obtain a third signal having a third frequency and synchronized with the second signal, and a synchronizing signal generating unit for generating a synchronizing signal which is adapted to synchronize the first signal with the second and third signals in accordance with a logical operation on the first, second and third signals. With this arrangement, the internal clock signals can be synchronized without using a reset signal. Consequently, neither wiring for supplying the reset signal nor a circuit for generating the reset signal are necessary.
摘要翻译：同步电路具有用于分割控制信号以获得具有第一频率的第一信号的第一信号产生单元，用于分配控制信号以获得具有第二频率的第二信号的第二信号产生单元，用于分配控制信号以获得具有第三频率并与第二信号同步的第三信号，以及同步信号产生单元，用于产生适于使第一信号与第二和第三信号同步的同步信号，该同步信号根据逻辑对第一，第二和第三信号进行操作。利用这种布置，可以在不使用复位信号的情况下同步内部时钟信号。因此，不需要用于提供复位信号的布线和用于产生复位信号的电路。

23. 发明授权

US5196738A Data driver circuit of liquid crystal display for achieving digital gray-scale 失效
标题翻译：用于实现数字灰度级的液晶显示器的数据驱动电路
公开(公告)号：US5196738A
公开(公告)日：1993-03-23
申请号：US766132
申请日：1991-09-27
申请人： Kazuhiro Takahara , Tadahisa Yamaguchi , Masami Oda , Hisashi Yamaguchi , Tetsuo Aoki , Fumitaka Asami
发明人： Kazuhiro Takahara , Tadahisa Yamaguchi , Masami Oda , Hisashi Yamaguchi , Tetsuo Aoki , Fumitaka Asami
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/2011 , G09G3/3648 , G09G3/3688 , G09G2310/027
摘要： A data driver circuit of TFT-LCD having a plurality of power source voltage terminals with different voltage levels, an output terminal for providing a voltage to the TFT-LCD, a plurality of analog switches with load resistances provided between one of the source voltage terminals and the output terminal and having a switching terminal, and a voltage selection circuit for transmitting an ON signal to a selected one or more of the respective switching terminals of the analog switches. When an individual analog switch is turned ON, the corresponding source voltage value is supplied to the output terminal of the driver circuit and when two or more analog switches are selectively turned on, a combination of the voltage levels of the respective source voltage is associated with those switches which are turned ON is produced as the driver circuit output voltage, thereby affording a greater number of gray levels as the driver circuit output voltage levels than the number of power source voltage levels.

24. 发明授权

US4400615A Programmable counter circuit 失效
标题翻译：可编程计数器电路
公开(公告)号：US4400615A
公开(公告)日：1983-08-23
申请号：US217386
申请日：1980-12-17
申请人： Fumitaka Asami , Osamu Takagi
发明人： Fumitaka Asami , Osamu Takagi
IPC分类号： H03K23/58 , H03K3/356 , H03K23/66 , G06F7/68
CPC分类号： H03K23/665 , H03K3/356104
摘要： In order to improve the operable frequency of a programmable counter circuit which serves as an N-step counter by loading an initial value N, load terminals of flip-flops of respective stages forming the counter circuit are sequentially cascade-connected via buffers and a load signal is applied to each of the load terminals from a load signal generator circuit. The load signal generator circuit includes a detector circuit which detects a specified value which is provided a short time before the initial value loading of the counter circuit and generates a detected output signal. The detected output signal is shifted by a shift register included in the load signal generator circuit which operates on the same clock signal as that which drives the counter circuit, thereby generating the load signal at the moment of the initial value loading of the counter circuit. In this case, for the duration of the load signal and a certain period of time subsequent thereto the application of the output from the detector circuit to the shift register is inhibited by a load control circuit included within the load signal generator circuit, thus preventing erroneous loading.
摘要翻译：为了通过加载初始值N来提高用作N步计数器的可编程计数器电路的可操作频率，构成计数器电路的各级的触发器的负载端子通过缓冲器和负载顺序级联信号从负载信号发生器电路施加到每个负载端子。负载信号发生器电路包括检测器电路，其检测在计数器电路的初始值加载之前短时间提供的指定值，并产生检测到的输出信号。检测到的输出信号被包含在负载信号发生器电路中的移位寄存器移位，该移位寄存器在与驱动计数器电路的时钟信号相同的时钟信号上工作，从而在计数器电路的初始值加载时产生负载信号。在这种情况下，在负载信号的持续时间和随后的一段时间内，由负载信号发生器电路中包括的负载控制电路禁止从检测器电路向移位寄存器的输出的应用，从而防止错误加载。

25. 发明授权

US4366398A Amplifier circuit 失效
标题翻译：放大器电路
公开(公告)号：US4366398A
公开(公告)日：1982-12-28
申请号：US201387
申请日：1980-07-17
申请人： Fumitaka Asami
发明人： Fumitaka Asami
IPC分类号： H03F3/16 , H03F3/34 , H03F3/345 , H03F3/72 , H03K19/0948 , H03K19/40
CPC分类号： H03F3/16 , H03F3/345 , H03F3/72
摘要： An amplifier circuit composed of two cascade-connected inverter stages, each of which consists of p channel and n channel transistors connected at their drains, n channel and p channel transistors which connect the gates of the, transistors of the first inverter to their respective drains by means of the control signal while said amplifier circuit is operated, and n channel and p channel transistors which connect the gates of both transistors of the first inverter respectively to specified potentials which set both transistors at the cut-off condition by means of the control signal while said amplifier circuit is not operated.
摘要翻译： PCT No.PCT / JP79 / 00285 Sec。 371日期1980年7月17日 102（e）日期1980年7月3日PCT申请日1979年11月6日PCT公布。出版物WO80 / 01124 日期为1980年5月29日。一个由两个级联连接的反相器级组成的放大器电路，每个放大器电路由在其漏极连接的p沟道和n沟道晶体管组成，n沟道和p沟道晶体管连接晶体管的栅极第一反相器通过控制信号在所述放大器电路被操作时到达它们各自的漏极，并且将n沟道和p沟道晶体管分别连接到第一反相器的两个晶体管的栅极到规定的两个晶体管的截止电位当所述放大器电路未被操作时借助于控制信号的条件。

26. 发明授权

US06965359B2 Method of driving plasma display panel by applying discharge sustaining pulses 失效
标题翻译：通过施加放电维持脉冲驱动等离子体显示面板的方法
公开(公告)号：US06965359B2
公开(公告)日：2005-11-15
申请号：US09966510
申请日：2001-09-28
申请人： Tomoyuki Ishii , Tadatsugu Hirose , Yoshikazu Kanazawa , Toshio Ueda , Tomokatsu Kishi , Shigetoshi Tomio , Fumitaka Asami
发明人： Tomoyuki Ishii , Tadatsugu Hirose , Yoshikazu Kanazawa , Toshio Ueda , Tomokatsu Kishi , Shigetoshi Tomio , Fumitaka Asami
IPC分类号： G09G3/20 , G09G3/292 , G09G3/293 , G09G3/294 , G09G3/296 , G09G3/298 , G09G3/299 , H01J17/49 , G09G3/28
CPC分类号： H01J11/28 , G09G3/2018 , G09G3/292 , G09G3/293 , G09G3/2932 , G09G3/294 , G09G3/2948 , G09G3/296 , G09G3/2983 , G09G3/299 , G09G2310/0205 , G09G2310/0218 , G09G2310/0221 , G09G2310/0224 , G09G2330/021 , H01J11/12 , H01J11/44 , H01J2211/444
摘要： Method for driving a plasma display panel. At least one first discharge sustaining pulse is applied to a first pair of display electrodes, and at least one second discharge sustaining pulse applied to an adjacent pair of display electrodes. The first and second discharge sustaining pulses are applied such that they are in the same phase as one another and/or such that a current in the first pair of display electrodes flows in the opposite direction from a current in the adjacent pair of display electrodes.
摘要翻译：驱动等离子体显示面板的方法至少一个第一放电维持脉冲被施加到第一对显示电极，并且至少一个第二放电维持脉冲施加到相邻的一对显示电极。施加第一和第二放电维持脉冲，使得它们彼此处于相同的相位和/或使得第一对显示电极中的电流与相邻的一对显示电极中的电流相反的方向流动。

27. 发明授权

US06781564B2 Display apparatus 失效
标题翻译：显示装置
公开(公告)号：US06781564B2
公开(公告)日：2004-08-24
申请号：US10320550
申请日：2002-12-17
申请人： Makoto Onozawa , Yuji Sano , Michitaka Ohsawa , Takashi Sasaki , Noboru Akiyama , Fumitaka Asami , Kazuo Yoshiikawa , Hitoshi Hirakawa , Tomokatsu Kishi , Toyoshi Kawada
发明人： Makoto Onozawa , Yuji Sano , Michitaka Ohsawa , Takashi Sasaki , Noboru Akiyama , Fumitaka Asami , Kazuo Yoshiikawa , Hitoshi Hirakawa , Tomokatsu Kishi , Toyoshi Kawada
IPC分类号： G09G328
CPC分类号： G09G3/2965 , G09G3/2927 , G09G3/293 , G09G3/294 , G09G3/296
摘要： A display apparatus includes a display panel including address electrodes and sustain electrodes crossing the address electrodes, with pixels being sandwiched between the address electrodes and the sustain electrodes. A sustain-electrode drive circuit selectively generates both sustain pulses and scan pulses and supplies them to the sustain electrodes. An address-electrode drive circuit generates address pulses based on a video signal and supplies the address pulses to the address electrodes. A control-signal generation circuit generates a control signal for controlling the sustain-electrode drive circuit to generate a selected one of the sustain pulses and the scan pulses and supplies the control signal to the sustain-electrode drive circuit. In order to display an image on the display panel, the sustain-electrode drive circuit both specifies addresses of pixels to be turned on and turns on the pixels at the specified addresses.
摘要翻译：显示装置包括显示面板，包括寻址电极和与寻址电极交叉的维持电极，像素被夹在寻址电极和维持电极之间。维持电极驱动电路选择性地产生维持脉冲和扫描脉冲，并将它们提供给维持电极。地址电极驱动电路基于视频信号产生寻址脉冲，并将地址脉冲提供给地址电极。控制信号生成电路生成用于控制维持电极驱动电路以产生维持脉冲和扫描脉冲中选择的一个的控制信号，并将控制信号提供给维持电极驱动电路。为了在显示面板上显示图像，维持电极驱动电路都指定要打开的像素的地址，并打开指定地址处的像素。

28. 发明授权

US06373452B1 Plasma display panel, method of driving same and plasma display apparatus 失效
标题翻译：等离子体显示面板，驱动方法和等离子体显示装置
公开(公告)号：US06373452B1
公开(公告)日：2002-04-16
申请号：US08690038
申请日：1996-07-31
申请人： Tomoyuki Ishii , Tadatsugu Hirose , Yoshikazu Kanazawa , Toshio Ueda , Tomokatsu Kishi , Shigetoshi Tomio , Fumitaka Asami
发明人： Tomoyuki Ishii , Tadatsugu Hirose , Yoshikazu Kanazawa , Toshio Ueda , Tomokatsu Kishi , Shigetoshi Tomio , Fumitaka Asami
IPC分类号： G09G328
CPC分类号： H01J11/28 , G09G3/2018 , G09G3/292 , G09G3/293 , G09G3/2932 , G09G3/294 , G09G3/2948 , G09G3/296 , G09G3/2983 , G09G3/299 , G09G2310/0205 , G09G2310/0218 , G09G2310/0221 , G09G2310/0224 , G09G2330/021 , H01J11/12 , H01J11/44 , H01J2211/444
摘要： An electrode drive circuit performs interlaced scanning, ensuring that the phases of the sustaining pulse in odd-numbered lines and even-numbered lines among L1 to L8 between surface discharge electrodes are the reverse of each other. With this, when either odd-numbered lines or even-numbered lines are displayed, the voltages applied between the electrodes of the undisplayed lines are at 0, eliminating the necessity for partitioning walls on the surface discharge electrodes. In surface discharge electrodes, X electrodes are provided on the two sides of a Y electrode and the area between the Y electrode and the X electrode on one side is assigned a display line at an odd-numbered frame, and the area between the Y electrode and the X electrode on the other side is assigned a display line in an even-numbered frame. Alternate areas between the surface discharge electrodes are assigned as blind lines and a discharge light emission in the blind lines is blocked or incident light to the blind lines from the outside is absorbed. Address electrodes are provided for each monochromatic pixel column and selectively connected with the pads above them, performing simultaneous selection of lines.
摘要翻译：电极驱动电路进行隔行扫描，确保表面放电电极之间的L1〜L8中的奇数行和偶数行中的维持脉冲的相位彼此相反。这样，当显示奇数行或偶数行时，施加在未显示行的电极之间的电压为0，消除了在表面放电电极上分隔壁的必要性。在表面放电电极中，X电极设置在Y电极的两侧，并且一侧的Y电极和X电极之间的区域被指定为奇数帧的显示线，并且Y电极并且在另一侧的X电极被分配有偶数帧中的显示行。表面放电电极之间的交替区域被分配为盲线，并且盲线中的放电发光被阻挡，或者从外部吸收到盲线的入射光。为每个单色像素列提供地址电极，并选择性地与其上的焊盘连接，执行行的同时选择。

29. 发明授权

US5898414A Display method for intermediate gray scale and display apparatus for expressing intermediate gray scale 失效
标题翻译：用于中间灰度显示方法和用于表示中间灰度的显示装置
公开(公告)号：US5898414A
公开(公告)日：1999-04-27
申请号：US865124
申请日：1997-05-30
申请人： Kenji Awamoto , Naoki Matsui , Tadatsugu Hirose , Fumitaka Asami
发明人： Kenji Awamoto , Naoki Matsui , Tadatsugu Hirose , Fumitaka Asami
IPC分类号： G09G3/20 , G09G3/28 , G09G3/288 , G09G3/291 , G09G3/294 , G09G3/296 , G09G3/298
CPC分类号： G09G3/2037 , G09G3/2029 , G09G2310/021 , G09G2310/0224 , G09G2310/0227 , G09G2320/0247 , G09G3/2803 , H04N5/70 , H04N7/012
摘要： A display apparatus permitting high resolution and a large number of gray-scale levels and causing indiscernible flicker has been disclosed. One frame is divided into or composed of j subframes, and light is produced according to a luminance level predetermined subframe by subframe in order to express intermediate gray-scale of a picture. Emphasis is put on the fact that display to be performed during each subframe within one frame can be controlled independently. An interlaced-scanning display is carried out during k subframes associated with low-order weighted bits out of j subframes, and a noninterlaced-scanning display is carried out during the other j-k subframes associated with high-order weighted bits. The ratio of an addressing scan time to a subframe associated with a small weight is large, and the ratio of an addressing scan time to a whole frame is very large. If the addressing scan time can be reduced as mentioned above, a great effect would be exerted. Moreover, the luminance levels to be determined in relation to the subframes during which interlaced-scanning display is carried out are so low that the influence of the reduction on a whole picture is limited.
摘要翻译：已经公开了允许高分辨率和大量灰度级并引起不明显的闪烁的显示装置。一帧被划分为j个子帧，或者由j个子帧组成，并且根据子帧逐个预定的亮度级产生光，以便表示图像的中间灰度。重点在于可以独立地控制在一帧内的每个子帧期间执行的显示。在与j个子帧中的低阶加权比特相关联的k个子帧期间执行隔行扫描显示，并且在与高阶加权比特相关联的其他j-k个子帧期间执行非隔行扫描显示。寻址扫描时间与小重量相关联的子帧的比例大，寻址扫描时间与整个帧的比例非常大。如果如上所述可以减少寻址扫描时间，则将产生很大的效果。此外，与执行隔行扫描显示的子帧相关的亮度水平确定得如此之低，使得整个图像上的缩小的影响受到限制。

30. 发明授权

US5680064A Level converter for CMOS 3V to from 5V 失效
标题翻译：用于CMOS 3V至5V的电平转换器
公开(公告)号：US5680064A
公开(公告)日：1997-10-21
申请号：US653973
申请日：1996-05-28
申请人： Satoru Masaki , Akinori Yamamoto , Fusao Seki , Fumitaka Asami , Kazuo Ohno , Masao Imai , Shinya Udo
发明人： Satoru Masaki , Akinori Yamamoto , Fusao Seki , Fumitaka Asami , Kazuo Ohno , Masao Imai , Shinya Udo
IPC分类号： G06F15/78 , G11C11/407 , H03K3/356 , H03K5/02 , H03K19/00 , H03K19/0185 , H03M1/76 , H03K19/0175 , H03K19/094
CPC分类号： H03K3/356104 , H03K3/356165
摘要： A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source. The level conversion circuit is supplied with power from the first driving power source, and converts an output signal of the first circuit system into an input signal of the second circuit system. The second circuit system drives a signal with level converted by being supplied with power from the second driving power source. Further, in the semiconductor integrated circuit, a bidirectional level conversion circuit and a signal control means are provided, and the first and the second driving power sources are wired in a lattice form in a semiconductor chip.
摘要翻译：第一级转换器设置有输入晶体管电路和输出晶体管电路。输入晶体管电路由第一电源供电，并根据输入信号输出互补信号。输出晶体管电路从第二电源供电，并放大并输出互补信号。第二电平转换器设置有脉冲发生电路和信号输出电路。脉冲发生电路由第一驱动电源供电，并产生单触发脉冲信号。信号输出电路由第二驱动电源供电，锁存单触发脉冲信号并输出信号。半导体集成电路设置有第一电路系统，电平转换电路和第二电路系统。第一电路系统通过从第一驱动电源供电来驱动。电平转换电路由第一驱动电源供电，并将第一电路系统的输出信号转换为第二电路系统的输入信号。第二电路系统通过从第二驱动电源供电而驱动具有电平转换的信号。此外，在半导体集成电路中，设置有双向电平转换电路和信号控制装置，并且第一和第二驱动电源以晶格形式布线在半导体芯片中。

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