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21. 发明申请

US20080040562A1 SYSTEMS AND METHODS FOR PROVIDING DISTRIBUTED AUTONOMOUS POWER MANAGEMENT IN A MEMORY SYSTEM 失效
标题翻译：用于在存储系统中提供分布式自动电源管理的系统和方法
公开(公告)号：US20080040562A1
公开(公告)日：2008-02-14
申请号：US11463483
申请日：2006-08-09
申请人： Kevin C. Gower , Robert B. Tremaine
发明人： Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/206 , G06F1/3225 , Y02D10/13 , Y02D10/14 , Y02D10/16
摘要： Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.
摘要翻译：在存储系统中提供分布式自主电源管理的系统和方法。实施例包括用于存储和检索用于处理系统的数据的存储器系统。存储器系统包括用于接收和响应存储器访问请求的存储器控制器，与存储器控制器通信的存储器总线，多个存储器件以及存储器控制器外部的控制单元。存储器设备经由存储器总线与存储器控制器通信，其中一个或多个存储器设备与组相关联。控制单元自主地管理存储器设备组内的功能。

22. 发明申请

US20070276976A1 SYSTEMS AND METHODS FOR PROVIDING DISTRIBUTED TECHNOLOGY INDEPENDENT MEMORY CONTROLLERS 失效
标题翻译：用于提供分布式技术独立存储器控制器的系统和方法
公开(公告)号：US20070276976A1
公开(公告)日：2007-11-29
申请号：US11420034
申请日：2006-05-24
申请人： Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F13/4243 , G06F13/4247
摘要： Systems and methods for providing distributed technology independent memory controllers. Systems include a computer memory system for storing and retrieving data. The system includes a memory bus, a main memory controller, one or more memory devices characterized by memory device protocols and signaling requirements, and one or more memory hub devices. The main memory controller is in communication with the memory bus for generating, receiving, and responding to memory access requests. The hub devices are in communication with the memory bus and with the memory devices for controlling the memory devices responsively to the memory access requests received from the main memory controller and for responding to the main memory controller with state or memory data. The main memory controller and the hub devices communicate via the memory bus in messages in a message format and protocol for indicating memory read, memory write, memory system power management and control that is independent of the memory device protocols and signaling requirements.
摘要翻译：提供分布式技术独立存储器控制器的系统和方法。系统包括用于存储和检索数据的计算机存储器系统。该系统包括存储器总线，主存储器控制器，以存储器件协议和信令要求为特征的一个或多个存储器件，以及一个或多个存储器集线器设备。主存储器控制器与存储器总线通信，用于生成，接收和响应存储器访问请求。集线器设备与存储器总线和存储器设备通信，用于响应于从主存储器控制器接收的存储器访问请求来控制存储器件并且用状态或存储器数据对主存储器控制器进行响应。主存储器控制器和集线器设备通过消息中的消息格式和协议通过存储器总线进行通信，用于指示独立于存储器件协议和信令要求的存储器读取，存储器写入，存储器系统电源管理和控制。

23. 发明授权

US08495328B2 Providing frame start indication in a memory system having indeterminate read data latency 有权
标题翻译：在具有不确定的读数据延迟的存储器系统中提供帧起始指示
公开(公告)号：US08495328B2
公开(公告)日：2013-07-23
申请号：US13397827
申请日：2012-02-16
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method for providing frame start indication that includes receiving a data transfer via a channel in a memory system. The receiving is in response to a request, and at an indeterminate time relative to the request. It is determined whether the data transfer includes a frame start indicator. The data transfer and “n” subsequent data transfers are captured in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers make up a data frame, where “n” is greater than zero.
摘要翻译：一种用于提供帧开始指示的方法，包括经由存储器系统中的信道接收数据传送。接收是响应于请求，并且在相对于请求的不确定的时间。确定数据传输是否包括帧起始指示符。响应于确定数据传输包括帧起始指示符，捕获数据传输和“n”个后续数据传输。数据传输和“n”个后续数据传输构成数据帧，其中“n”大于零。

24. 发明授权

US08493801B2 Strobe offset in bidirectional memory strobe configurations 有权
标题翻译：双向内存选通配置中的频闪偏移
公开(公告)号：US08493801B2
公开(公告)日：2013-07-23
申请号：US13570430
申请日：2012-08-09
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

25. 发明申请

US20120300564A1 Strobe Offset in Bidirectional Memory Strobe Configurations 有权
标题翻译：双向内存频闪配置中的频闪偏移
公开(公告)号：US20120300564A1
公开(公告)日：2012-11-29
申请号：US13570430
申请日：2012-08-09
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译：一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

26. 发明授权

US08145868B2 Method and system for providing frame start indication in a memory system having indeterminate read data latency 有权
标题翻译：在具有不确定的读数据延迟的存储器系统中提供帧起始指示的方法和系统
公开(公告)号：US08145868B2
公开(公告)日：2012-03-27
申请号：US11843150
申请日：2007-08-22
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method and system for providing frame start indication in a memory system having indeterminate read data latency. The method includes receiving a data transfer and determining if the data transfer includes a frame start indicator. The method also includes capturing the data transfer and “n” subsequent data transfers in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers comprise a data frame.
摘要翻译：一种用于在具有不确定的读数据延迟的存储器系统中提供帧起始指示的方法和系统。该方法包括接收数据传输并确定数据传输是否包括帧起始指示符。响应于确定数据传输包括帧起始指示符，该方法还包括捕获数据传输和“n”次后续数据传输。数据传输和“n”个后续数据传输包括数据帧。

27. 发明授权

US07685392B2 Providing indeterminate read data latency in a memory system 失效
标题翻译：在存储器系统中提供不确定的读取数据延迟
公开(公告)号：US07685392B2
公开(公告)日：2010-03-23
申请号：US11289193
申请日：2005-11-28
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/18 , G06F13/372 , G06F13/376
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received and storing it into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle, and in response thereto the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. The upstream data packet is selectively transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.
摘要翻译：一种用于在存储器系统中提供不确定的读取数据延迟的方法。该方法包括确定本地数据分组是否已被接收并将其存储到缓冲设备中。该方法还包括确定缓冲器装置是否包含数据包，并确定是否经由上游信道将数据包发送到存储器控制器的上游驱动器是空闲的，并且响应于此数据包被发送到上游驱动器。该方法还包括确定是否已经接收到上游数据分组，并且上游驱动器不空闲，则上游数据分组被存储到缓冲设备中。上游数据包被选择性地发送到上游驱动器。如果上游驱动程序不空闲，那么正在进行的任何数据分组都将继续传输到上游驱动程序。

28. 发明授权

US07627732B2 Memory systems for automated computing machinery 失效
标题翻译：自动计算机的存储系统
公开(公告)号：US07627732B2
公开(公告)日：2009-12-01
申请号：US12102034
申请日：2008-04-14
申请人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H04L12/50 , H04Q11/00
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译：提供体现在机器可读介质中的设计结构。设计结构的实施例包括存储器系统，包括：存储器控制器; 一个内存总线终端; 连接存储器控制器，存储器总线终端器和至少一个存储器模块的高速存储器总线; 和所述至少一个存储器模块，所述存储器模块包括至少一个存储器集线器设备，由所述存储器集线器设备服务的高速随机存取存储器，两个总线信号端口以及在所述存储器模块上制造的所述高速存储器总线的段以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器设备。

29. 发明授权

US07277988B2 System, method and storage medium for providing data caching and data compression in a memory subsystem 失效
标题翻译：用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质
公开(公告)号：US07277988B2
公开(公告)日：2007-10-02
申请号：US10977846
申请日：2004-10-29
申请人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
发明人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译：包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

30. 发明申请

US20130262792A1 MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS 审中-公开
标题翻译：记忆体系中动态变化频率的记忆体设备支持
公开(公告)号：US20130262792A1
公开(公告)日：2013-10-03
申请号：US13431108
申请日：2012-03-27
申请人： John E. Barth, JR. , Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
发明人： John E. Barth, JR. , Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.
摘要翻译：实施例是一种方法，包括将第一组存储器件参数写入存储器件中的第一模式寄存器，其中第一组存储器件参数对应于第一频率，在存储器件操作期间监视存储器系统的选定参数在第一频率处，并且预测存储器设备将在第一频率之后操作的第二频率，所述预测基于所监视的所选择的参数。该方法还包括将第二组存储器件参数写入存储器件中的第二模式寄存器，在与存储器件相关联的存储器控制器处接收频率改变请求，频率改变请求以新频率操作并更新第一模式寄存器，响应于新频率等于第二频率，来自第二模式寄存器的第二组存储器件参数。

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