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1. 发明申请

US20130262792A1 MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS 审中-公开
标题翻译：记忆体系中动态变化频率的记忆体设备支持
公开(公告)号：US20130262792A1
公开(公告)日：2013-10-03
申请号：US13431108
申请日：2012-03-27
申请人： John E. Barth, JR. , Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
发明人： John E. Barth, JR. , Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.
摘要翻译：实施例是一种方法，包括将第一组存储器件参数写入存储器件中的第一模式寄存器，其中第一组存储器件参数对应于第一频率，在存储器件操作期间监视存储器系统的选定参数在第一频率处，并且预测存储器设备将在第一频率之后操作的第二频率，所述预测基于所监视的所选择的参数。该方法还包括将第二组存储器件参数写入存储器件中的第二模式寄存器，在与存储器件相关联的存储器控制器处接收频率改变请求，频率改变请求以新频率操作并更新第一模式寄存器，响应于新频率等于第二频率，来自第二模式寄存器的第二组存储器件参数。

2. 发明申请

US20130262791A1 HOST-SIDE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS 审中-公开
标题翻译：内存系统动态更改频率的主机支持
公开(公告)号：US20130262791A1
公开(公告)日：2013-10-03
申请号：US13430807
申请日：2012-03-27
申请人： Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
发明人： Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： G06F12/00
CPC分类号： G11C29/023 , G06F1/324 , G06F1/3275 , G06F13/1689 , G11C29/028 , Y02D10/126 , Y02D10/14
摘要： An embodiment is a method for operating a memory system, the method including storing initial calibration values for each of a first frequency and second frequency for a memory device, performing a periodic calibration to determine a calibration update value for operation of the memory device at the first frequency, combining the calibration update value with the initial calibration value for the first frequency to provide an updated calibration for operation of the memory device at an operating frequency of the first frequency and receiving a frequency change request at a memory controller associated with the memory device. The method further includes blocking traffic to the memory device, adjusting operating frequency to the second frequency while the memory device remains powered, combining the calibration update value with the initial calibration value for the second frequency for operation at the second frequency and enabling traffic to the memory device.
摘要翻译：一个实施例是用于操作存储器系统的方法，该方法包括存储用于存储器件的第一频率和第二频率中的每一个的初始校准值，执行周期性校准以确定用于在存储器装置的操作的校准更新值将所述校准更新值与所述第一频率的初始校准值组合，以提供用于在所述第一频率的操作频率下操作所述存储器件的更新校准，并且在与所述存储器相关联的存储器控制器处接收频率改变请求设备。该方法还包括阻止对存储器件的流量，在存储器件保持通电的同时将操作频率调整到第二频率，将校准更新值与用于第二频率的第二频率的初始校准值相组合，并使流量达到存储设备。

3. 发明授权

US07487397B2 Method for cache correction using functional tests translated to fuse repair 失效
标题翻译：使用功能测试翻译保险丝修复的缓存校正方法
公开(公告)号：US07487397B2
公开(公告)日：2009-02-03
申请号：US11260562
申请日：2005-10-27
申请人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
发明人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.
摘要翻译：一种通过操作微处理器来执行利用高速缓冲存储器的功能测试程序来校正诸如高速缓存存储器的微处理器的存储阵列中的缺陷的方法，在功能测试程序期间收集跟踪阵列中的故障数据，使用故障数据在高速缓冲存储器中定位缺陷，以及通过设置保险丝将该位置的访问请求重新路由到冗余阵列来修复缺陷。故障数据可能包括错误综合征和故障地址。功能测试过程创建随机高速缓存访问序列，其使用基于随机种子的测试模式在高速缓冲存储器中引起变化的流量负载。功能测试程序可以在完成设置一些保险丝的微处理器的非功能性内置自检之后完成。

4. 发明申请

US20090083579A1 METHOD FOR CACHE CORRECTION USING FUNCTIONAL TESTS TRANSLATED TO FUSE REPAIR 失效
标题翻译：使用翻译成保险丝修复功能的测试方法进行高速缓存校正
公开(公告)号：US20090083579A1
公开(公告)日：2009-03-26
申请号：US12325272
申请日：2008-12-01
申请人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
发明人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
IPC分类号： G06F11/07
CPC分类号： G06F11/2236
摘要： A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.
摘要翻译：一种通过操作微处理器来执行利用高速缓冲存储器的功能测试程序来校正诸如高速缓存存储器的微处理器的存储阵列中的缺陷的方法，在功能测试程序期间收集跟踪阵列中的故障数据，使用故障数据在高速缓冲存储器中定位缺陷，以及通过设置保险丝将该位置的访问请求重新路由到冗余阵列来修复缺陷。故障数据可能包括错误综合征和故障地址。功能测试过程创建随机高速缓存访问序列，其使用基于随机种子的测试模式在高速缓冲存储器中引起变化的流量负载。功能测试程序可以在完成设置一些保险丝的微处理器的非功能性内置自检之后完成。

5. 发明申请

US20090006916A1 METHOD FOR CACHE CORRECTION USING FUNCTIONAL TESTS TRANSLATED TO FUSE REPAIR 审中-公开
公开(公告)号：US20090006916A1
公开(公告)日：2009-01-01
申请号：US12207496
申请日：2008-09-09
申请人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
发明人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
IPC分类号： G06F11/26
CPC分类号： G06F11/2236
摘要： A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

6. 发明授权

US07770067B2 Method for cache correction using functional tests translated to fuse repair 失效
标题翻译：使用功能测试翻译保险丝修复的缓存校正方法
公开(公告)号：US07770067B2
公开(公告)日：2010-08-03
申请号：US12325272
申请日：2008-12-01
申请人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
发明人： Walter R. Lockwood , Ryan J. Pennington , Hugh Shen , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.
摘要翻译：一种通过操作微处理器来执行利用高速缓冲存储器的功能测试程序来校正诸如高速缓存存储器的微处理器的存储阵列中的缺陷的方法，在功能测试程序期间收集跟踪阵列中的故障数据，使用故障数据在高速缓冲存储器中定位缺陷，以及通过设置保险丝将该位置的访问请求重新路由到冗余阵列来修复缺陷。故障数据可能包括错误综合征和故障地址。功能测试过程创建随机高速缓存访问序列，其使用基于随机种子的测试模式在高速缓冲存储器中引起变化的流量负载。功能测试程序可以在完成设置一些保险丝的微处理器的非功能性内置自检之后完成。

7. 发明申请

US20120054544A1 Non-Disruptive Hardware Change 失效
标题翻译：非破坏性硬件更改
公开(公告)号：US20120054544A1
公开(公告)日：2012-03-01
申请号：US12862492
申请日：2010-08-24
申请人： Michael S. Floyd , Ryan J. Pennington , Harmony L. Prince , Kevin F. Reick , David D. Sanner
发明人： Michael S. Floyd , Ryan J. Pennington , Harmony L. Prince , Kevin F. Reick , David D. Sanner
IPC分类号： G06F9/00 , G06F11/20
CPC分类号： G06F11/2043 , G06F11/203 , G06F11/2035
摘要： A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.
摘要翻译：一种用于在不中断在数据处理系统上执行的处理的情况下改变数据处理系统中的硬件的方法，系统和计算机程序产品。可能需要对数据处理系统中的所选部分硬件进行硬件更改，例如修复硬件错误或实现系统更新。响应于要求硬件对硬件的所选部分的改变的确定，所选择的部分执行的处理从硬件的所选部分移动到硬件的替代部分。硬件更改应用于硬件的选定部分。在应用硬件更改之后，硬件的所选部分返回供数据处理系统使用。

8. 发明申请

US20130318364A1 PROCESSOR NOISE MITIGATION USING DIFFERENTIAL CRITICAL PATH MONITORING 有权
标题翻译：使用差分关键路径监测的处理器噪声减轻
公开(公告)号：US20130318364A1
公开(公告)日：2013-11-28
申请号：US13479797
申请日：2012-05-24
申请人： Robert W. Berry, JR. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
发明人： Robert W. Berry, JR. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
IPC分类号： G06F1/26
CPC分类号： G06F1/28 , G06F1/26 , G06F11/3062
摘要： An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
摘要翻译：提供了一种处理器电源噪声抑制方法。在一个方面，该方法包括可操作地耦合到处理器以执行程序操作的中央计算单元。该方法还包括校准电路，其适于确定要用于通过使用检测电路动态执行的比较的处理器上的第一阈值。一种检测电路，适用于动态地监视处理器的系统操作并指示是否违反了第一阈值，还提供了一种适于在一个或多个电压感测测量违反第一阈值时防止电压下降的计数电路。

9. 发明授权

US09164563B2 Processor noise mitigation using differential critical path monitoring 有权
标题翻译：使用差分关键路径监控的处理器噪声抑制
公开(公告)号：US09164563B2
公开(公告)日：2015-10-20
申请号：US13479797
申请日：2012-05-24
申请人： Robert W. Berry, Jr. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
发明人： Robert W. Berry, Jr. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
IPC分类号： G06F1/28 , G06F1/26 , G06F11/30
CPC分类号： G06F1/28 , G06F1/26 , G06F11/3062
摘要： An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
摘要翻译：提供了一种处理器电源噪声抑制方法。在一个方面，该方法包括可操作地耦合到处理器以执行程序操作的中央计算单元。该方法还包括校准电路，其适于确定要用于通过使用检测电路动态执行的比较的处理器上的第一阈值。一种检测电路，适用于动态地监视处理器的系统操作并指示是否违反了第一阈值，还提供了一种适于在一个或多个电压感测测量违反第一阈值时防止电压下降的计数电路。

10. 发明授权

US08650431B2 Non-disruptive hardware change 失效
标题翻译：无中断硬件的变化
公开(公告)号：US08650431B2
公开(公告)日：2014-02-11
申请号：US12862492
申请日：2010-08-24
申请人： Michael S. Floyd , Ryan J. Pennington , Harmony L. Prince , Kevin F. Reick , David D. Sanner
发明人： Michael S. Floyd , Ryan J. Pennington , Harmony L. Prince , Kevin F. Reick , David D. Sanner
IPC分类号： G06F11/00
CPC分类号： G06F11/2043 , G06F11/203 , G06F11/2035
摘要： A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.
摘要翻译：一种用于在不中断在数据处理系统上执行的处理的情况下改变数据处理系统中的硬件的方法，系统和计算机程序产品。可能需要对数据处理系统中的所选部分硬件进行硬件更改，例如修复硬件错误或实现系统更新。响应于要求硬件对硬件的所选部分的改变的确定，所选择的部分执行的处理从硬件的所选部分移动到硬件的替代部分。硬件更改应用于硬件的选定部分。在应用硬件更改之后，硬件的所选部分返回供数据处理系统使用。

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