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21. 发明申请

US20100006906A1 Semiconductor device, single crystalline silicon wafer, and single crystalline silicon ingot 审中-公开
标题翻译：半导体器件，单晶硅晶片和单晶硅锭
公开(公告)号：US20100006906A1
公开(公告)日：2010-01-14
申请号：US12458500
申请日：2009-07-14
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L29/04
CPC分类号： H01L27/0203 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L29/045 , H01L29/66628
摘要： A semiconductor device includes a single crystalline substrate and an active region defined in the single crystalline substrate, wherein a major axis direction of the active region is aligned with a family direction.
摘要翻译：半导体器件包括单晶衬底和限定在单晶衬底中的有源区，其中有源区的长轴方向与<0,1,1>族方向对齐。

22. 发明申请

US20090170254A1 Method of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090170254A1
公开(公告)日：2009-07-02
申请号：US12343134
申请日：2008-12-23
申请人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
发明人： Hwa-Sung Rhee , Ho Lee , Myung-Sun Kim , Ji-Hye Yi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.
摘要翻译：在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。在基板和第一和第二栅电极上形成具有第一应力的层。掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。在凹部中形成具有第二应力的图案。

23. 发明申请

US20080142474A1 Methods of forming a pattern and methods of manufacturing a capacitor using the same 失效
标题翻译：形成图案的方法和使用其制造电容器的方法
公开(公告)号：US20080142474A1
公开(公告)日：2008-06-19
申请号：US12002052
申请日：2007-12-14
申请人： Kyoung-Mi Kim , Young-Ho Kim , Myung-Sun Kim , Jae-Ho Kim , Chang-Ho Lee , Seok Han
发明人： Kyoung-Mi Kim , Young-Ho Kim , Myung-Sun Kim , Jae-Ho Kim , Chang-Ho Lee , Seok Han
IPC分类号： H01G4/00
CPC分类号： H01G13/00 , H01G4/33 , H01L27/10814 , H01L27/10852 , H01L28/91
摘要： In a method of forming a pattern and a method of forming a capacitor, an oxide layer pattern having an opening is formed on a substrate. A conductive layer is formed on the oxide layer pattern and the bottom and sidewalls of the opening. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern including a siloxane polymer. The conductive layer on the oxide layer pattern is selectively removed using the buffer layer pattern as an etching mask. A conductive pattern having a cylindrical shape can be formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.
摘要翻译：在形成图案的方法和形成电容器的方法中，在基板上形成具有开口的氧化物层图案。在氧化物层图案和开口的底部和侧壁上形成导电层。在具有导电层的开口中形成缓冲层图案，缓冲层图案包括硅氧烷聚合物。使用缓冲层图案作为蚀刻掩模，选择性地去除氧化物层图案上的导电层。可以在基板上形成具有圆柱形状的导电图案。形成图案的方法可以简化电容器和半导体器件的制造工艺，并且可以提高它们的效率。

24. 发明授权

US08426916B2 Semiconductor integrated circuit devices having different thickness silicon-germanium layers 有权
标题翻译：具有不同厚度的硅 - 锗层的半导体集成电路器件
公开(公告)号：US08426916B2
公开(公告)日：2013-04-23
申请号：US13476121
申请日：2012-05-21
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/36
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。第二SiGe外延层直接形成在第一SiGe外延层上，以使用不同于第一硅源气体的第二硅源气体来进一步填充源极/漏极沟槽。

25. 发明授权

US08207033B2 Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby 有权
标题翻译：在半导体集成电路器件上制造不同厚度的硅 - 锗层的方法和由此制造的半导体集成电路器件
公开(公告)号：US08207033B2
公开(公告)日：2012-06-26
申请号：US12419698
申请日：2009-04-07
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

26. 发明申请

US20150024587A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150024587A1
公开(公告)日：2015-01-22
申请号：US14277330
申请日：2014-05-14
申请人： Kyoungmi Kim , Myung-Sun Kim , Jaeho Kim , Hyounghee Kim , Namuk Choi , Jungsik Choi
发明人： Kyoungmi Kim , Myung-Sun Kim , Jaeho Kim , Hyounghee Kim , Namuk Choi , Jungsik Choi
IPC分类号： H01L21/768 , H01L21/027
CPC分类号： H01L21/76879 , H01L21/0274 , H01L21/31144 , H01L21/32139 , H01L21/76807 , H01L21/76838 , H01L27/11548 , H01L27/11575 , H01L2221/1021
摘要： A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern.
摘要翻译：提供一种制造半导体器件的方法。在基板上形成蚀刻靶层。在蚀刻靶层上形成光致抗蚀剂层。使用第一光掩模进行第一曝光处理，以在光致抗蚀剂层中形成多个第一照射图案。第一光掩模包括多个第一透射区域。每个第一透射区域具有不同的透光率。使用第二光掩模进行第二曝光处理，以在光致抗蚀剂层中形成多个第二照射图案。第二光掩模包括多个第二透射区域。每个第二透射区域具有不同的透光率。通过从光致抗蚀剂层去除多个第一次照射和第二次照射的图案，从光致抗蚀剂层形成光刻胶图案。通过使用光致抗蚀剂图案蚀刻蚀刻目标层，从蚀刻目标层形成下部结构。

27. 发明授权

US08871423B2 Photoresist composition for fabricating probe array, method of fabricating probe array using the photoresist composition, composition for photosensitive type developed bottom anti-reflective coating, fabricating method of patterns using the same and fabricating method of semiconductor device using the same 有权
标题翻译：用于制造探针阵列的光致抗蚀剂组合物，使用光致抗蚀剂组合物制造探针阵列的方法，用于感光型显影底部抗反射涂层的组合物，使用其的图案的制造方法和使用其的半导体器件的制造方法
公开(公告)号：US08871423B2
公开(公告)日：2014-10-28
申请号：US13015869
申请日：2011-01-28
申请人： Hyo-Jin Yun , Jae-Ho Kim , Young-Ho Kim , Boo-Deuk Kim , Jin-A Ryu , Myung-Sun Kim , Se-Kyung Baek , Soo-Kyung Kim , Ji-Yun Ham
发明人： Hyo-Jin Yun , Jae-Ho Kim , Young-Ho Kim , Boo-Deuk Kim , Jin-A Ryu , Myung-Sun Kim , Se-Kyung Baek , Soo-Kyung Kim , Ji-Yun Ham
IPC分类号： G03F7/004 , G03F7/38 , C07C303/32 , C07C309/06 , C07C309/12 , G03F7/039 , G03F7/20
CPC分类号： G03F7/004 , C07C303/32 , C07C309/06 , C07C309/12 , G03F7/0045 , G03F7/0397 , G03F7/20 , Y10S430/122 , Y10S430/123
摘要： A photoresist composition for fabricating a probe array is provided. The photoresist composition includes a photoacid generator having an onium salt and an i-line reactive sensitizer.
摘要翻译：提供了用于制造探针阵列的光致抗蚀剂组合物。光致抗蚀剂组合物包括具有鎓盐和i线反应性敏化剂的光酸产生剂。

28. 发明授权

US07736527B2 Siloxane polymer compositions and methods of manufacturing a capacitor using the same 失效
标题翻译：硅氧烷聚合物组合物及其制造方法
公开(公告)号：US07736527B2
公开(公告)日：2010-06-15
申请号：US12008215
申请日：2008-01-09
申请人： Kyoung-Mi Kim , Myung-Sun Kim , Young-Ho Kim
发明人： Kyoung-Mi Kim , Myung-Sun Kim , Young-Ho Kim
IPC分类号： H01G4/01 , C08G77/50 , B05D5/12
CPC分类号： C08G77/20 , H01L21/02126 , H01L21/02216 , H01L21/02282 , H01L21/3122 , H01L21/32115 , H01L21/32139 , H01L28/91
摘要： Siloxane polymer compositions and methods of manufacturing a capacitor are described. In some embodiments, a mold layer pattern is formed on a substrate having a conductive structure, and the mold layer pattern has an opening to expose the conductive structure. A conductive layer is formed on the substrate. A buffer layer pattern is formed on the conductive layer formed in the opening. The buffer layer pattern includes a siloxane polymer represented by the following Chemical Formula 1. The conductive layer is selectively removed to form a lower electrode. The mold layer pattern and the buffer layer pattern are removed. A dielectric layer and an upper electrode are formed on the substrate to form a capacitor. The methods may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.
摘要翻译：描述硅氧烷聚合物组合物和制造电容器的方法。在一些实施例中，在具有导电结构的基底上形成模具层图案，并且模具层图案具有露出导电结构的开口。在基板上形成导电层。在形成在开口中的导电层上形成缓冲层图案。缓冲层图案包括由以下化学式1表示的硅氧烷聚合物。选择性地除去导电层以形成下电极。去除模层图案和缓冲层图案。在基板上形成电介质层和上电极，形成电容器。这些方法可以简化电容器和半导体器件的制造工艺，并且可以提高它们的效率。

29. 发明申请

US20060196648A1 Heat dissipating fin for use in heat exchanger 审中-公开
标题翻译：散热片用于热交换器
公开(公告)号：US20060196648A1
公开(公告)日：2006-09-07
申请号：US11154369
申请日：2005-06-16
申请人： Myung-Sun Kim
发明人： Myung-Sun Kim
IPC分类号： F28D1/04
CPC分类号： F28D1/0477 , F28F1/32 , F28F2225/00
摘要： The invention relates to a heat dissipating fin of a heat exchanger, more particularly, which is designed to facilitate coupling the heat dissipating fin with a refrigerant pipe in an assembling process of a heat exchanger as well as to improve heat dissipating efficiency. According to an aspect of the invention for realizing the above objects, there is provided a heat dissipating fin 20 for used with a heat exchanger, which includes a refrigerant pipe 10 and the heat dissipating fin 20 coupled with the refrigerant pipe 10. The heat dissipating fin 20 has slits 21 formed therein in series for allowing U-shaped bends 11 of the refrigerant pipe 10 to simultaneously pass through the slits 21, whereby the bends 11 of the refrigerant pipe 20 formed by successively bending the refrigerant pipe 10 into a serpentine configuration are inserted into the slits 21 at the same time so as to couple the heat dissipating fin 20 with the refrigerant pipe 10.
摘要翻译：本发明涉及一种热交换器的散热翅片，更具体地说，其特征在于，其设计成在热交换器的组装过程中有利于将散热翅片与制冷剂管连接，并提高散热效率。根据用于实现上述目的的本发明的一个方面，提供了一种与热交换器一起使用的散热片20，其包括制冷剂管10和与制冷剂管10连接的散热片20。散热片20具有形成在其中的狭缝21，其允许制冷剂管10的U形弯曲部11同时通过狭缝21，由此通过将制冷剂管10连续弯曲而形成的制冷剂管20的弯曲部11 蛇形结构同时插入狭缝21中，以将散热片20与制冷剂管10连接。

30. 发明授权

US09142455B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09142455B2
公开(公告)日：2015-09-22
申请号：US14277330
申请日：2014-05-14
申请人： Kyoungmi Kim , Myung-Sun Kim , Jaeho Kim , Hyounghee Kim , Namuk Choi , Jungsik Choi
发明人： Kyoungmi Kim , Myung-Sun Kim , Jaeho Kim , Hyounghee Kim , Namuk Choi , Jungsik Choi
IPC分类号： H01L21/768 , H01L21/027
CPC分类号： H01L21/76879 , H01L21/0274 , H01L21/31144 , H01L21/32139 , H01L21/76807 , H01L21/76838 , H01L27/11548 , H01L27/11575 , H01L2221/1021
摘要： A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern.
摘要翻译：提供一种制造半导体器件的方法。在基板上形成蚀刻靶层。在蚀刻靶层上形成光致抗蚀剂层。使用第一光掩模进行第一曝光处理，以在光致抗蚀剂层中形成多个第一照射图案。第一光掩模包括多个第一透射区域。每个第一透射区域具有不同的透光率。使用第二光掩模进行第二曝光处理，以在光致抗蚀剂层中形成多个第二照射图案。第二光掩模包括多个第二透射区域。每个第二透射区域具有不同的透光率。通过从光致抗蚀剂层去除多个第一次照射和第二次照射的图案，从光致抗蚀剂层形成光刻胶图案。通过使用光致抗蚀剂图案蚀刻蚀刻目标层，从蚀刻目标层形成下部结构。

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