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21. 发明授权

US07096277B2 Distributed lookup based on packet contents 有权
标题翻译：基于分组内容的分布式查找
公开(公告)号：US07096277B2
公开(公告)日：2006-08-22
申请号：US10214984
申请日：2002-08-07
申请人： Donald F. Hooper
发明人： Donald F. Hooper
IPC分类号： G06F15/173
CPC分类号： H04L69/22 , H04L69/12 , Y10S707/99936
摘要： The disclosure includes description of a technique for use in looking-up data based on content of a packet received over a network. The technique includes receiving a lookup value based on the received packet, searching a first memory using at least a portion of the lookup value, and if the searching the first memory fails, searching a second memory, having a lower latency than the first memory, using at least a portion of the lookup value.
摘要翻译：本公开包括基于通过网络接收的分组的内容用于查找数据的技术的描述。该技术包括基于接收的分组接收查找值，使用查找值的至少一部分来搜索第一存储器，并且如果搜索第一存储器失败，则搜索具有比第一存储器更低的等待时间的第二存储器，使用查找值的至少一部分。

22. 发明授权

US5212650A Procedure and data structure for synthesis and transformation of logic circuit designs 失效
标题翻译：逻辑电路设计的合成与转换的程序和数据结构
公开(公告)号：US5212650A
公开(公告)日：1993-05-18
申请号：US393107
申请日：1989-08-03
申请人： Donald F. Hooper , Snehamay Kundu
发明人： Donald F. Hooper , Snehamay Kundu
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , Y10S706/921
摘要： A procedure is described for the synthesis and transformation of a logic circuit design, provided by the designers, into a database capable of being used to fabricate the actual circuit. The procedure involves the use of model instances which represent the use of circuit components. The original model instances can be associated with groups of rules that determine resulting configurations of generally different model instances or groups of model instances. The rules are tested and, in the presence of a `true` result, a new model instance (or model instances) can replace one or more original model instances in the data base. The rules associated with a model type (or definition) are rules derived by a design model engineer and can include coupled model instances. The rules can be associated with model definitions, as well as model instances. The data structures associated with each model instance indicate the model interface as well as the model interface port and permit a path to followed in the circuit in either the forward or the reverse signal direction. The model instances reside within model definitions which reside with design data in hierarchical form. The rules controlling the synthesis and transformation of the circuit are contained in a separate hierarchy of data structures or knowledge structures to which reference can be made by design data structures.
摘要翻译：描述了将由设计者提供的逻辑电路设计的合成和转换的数据库用于制造实际电路的程序。该过程涉及使用表示使用电路组件的模型实例。原始模型实例可以与确定一般不同的模型实例或模型实例组的结果组的规则组相关联。测试规则，并且在存在“真实”结果的情况下，新的模型实例（或模型实例）可以替换数据库中的一个或多个原始模型实例。与模型类型（或定义）相关联的规则是由设计模型工程师派生的规则，并且可以包括耦合的模型实例。规则可以与模型定义以及模型实例相关联。与每个模型实例相关联的数据结构指示模型接口以及模型接口端口，并允许在正向或反向信号方向上在电路中跟随的路径。模型实例驻留在以分层形式存在于设计数据的模型定义中。控制电路的合成和转换的规则包含在数据结构或知识结构的单独分层中，可以通过设计数据结构进行参考。

23. 发明授权

US4794527A Microprogrammed data processing system using latch circuits to access different control stores with the same instruction at different times 失效
标题翻译：微程序数据处理系统使用锁存电路在不同时间以相同的指令访问不同的控制存储
公开(公告)号：US4794527A
公开(公告)日：1988-12-27
申请号：US823804
申请日：1986-01-29
申请人： Robert E. Stewart , Donald F. Hooper
发明人： Robert E. Stewart , Donald F. Hooper
IPC分类号： G06F9/22 , G06F9/28 , G06F9/38
CPC分类号： G06F9/28 , G06F9/223
摘要： A microprogrammed data processing system uses a plurality of control stores to control the data processing system in response to a macroinstruction sequence. Between each control store is a latch element resulting in a given address being applied to each control store at different system clock cycles. The corresponding microinstruction segment from each control store is therefore provided at different clock cycles, making it possible to coordinate the microinstruction segment with the corresponding flow of data through the central processing unit. The use of a plurality of control stores can reduce the number of gate elements needed to delay microinstruction segments.
摘要翻译：微程序数据处理系统使用多个控制存储器来响应宏指令序列来控制数据处理系统。在每个控制存储器之间是一个锁存元件，导致在不同的系统时钟周期将给定的地址应用于每个控制存储器。因此，来自每个控制存储器的对应微指令段在不同的时钟周期提供，使得可以通过中央处理单元将微指令段与对应的数据流协调。使用多个控制存储器可以减少延迟微指令段所需的门元件的数量。

24. 发明授权

US07684970B2 Graphical user interface for use during processor simulation 失效
标题翻译：在处理器模拟期间使用的图形用户界面
公开(公告)号：US07684970B2
公开(公告)日：2010-03-23
申请号：US10877922
申请日：2004-06-25
申请人： Donald F. Hooper , Eric Walker , Dennis Rivard , Mark B. Rosenbluth
发明人： Donald F. Hooper , Eric Walker , Dennis Rivard , Mark B. Rosenbluth
IPC分类号： G06F9/44 , G06F3/00
CPC分类号： G06F11/3664 , G06F11/3636
摘要： In accordance with one exemplary embodiment, the present disclosure includes a method for executing application software during a simulation that models a processor for which the application software was developed. The method may include capturing results of the simulation to produce a simulation history. The method may also include providing a graphical user interface (GUI) that includes one or more cross-linked packet-centric views of the simulation history for packets operated on by the application software during the simulation. The cross-linked packet-centric views may include a packet status list GUI, a packet event list GUI, a packet dataflow GUI, a thread list GUI, and a thread history GUI. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：根据一个示例性实施例，本公开包括一种用于在仿真期间执行应用软件的方法，其对开发应用软件的处理器进行建模。该方法可以包括捕获模拟的结果以产生模拟历史。该方法还可以包括提供图形用户界面（GUI），其包括在模拟期间由应用软件操作的分组的模拟历史的一个或多个以交叉分组为中心的视图。以交叉分组为中心的视图可以包括分组状态列表GUI，分组事件列表GUI，分组数据流GUI，线程列表GUI和线程历史GUI。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

25. 发明授权

US07515588B2 Method and apparatus to support a large internet protocol forwarding information base 有权
标题翻译：支持大型互联网协议转发信息库的方法和装置
公开(公告)号：US07515588B2
公开(公告)日：2009-04-07
申请号：US10804485
申请日：2004-03-18
申请人： Uday R. Naik , Alok Kumar , Eswar Eduri , Donald F. Hooper
发明人： Uday R. Naik , Alok Kumar , Eswar Eduri , Donald F. Hooper
IPC分类号： H04L12/28 , H04L12/56 , G06F7/00
CPC分类号： H04L45/54 , H04L45/04 , H04L45/742 , H04L45/745 , H04L45/7457 , Y10S707/99942
摘要： Method and apparatus to support a large Internet Protocol Forwarding Information Base. A packet is received at a network device, the packet including a destination address. A table is indexed into using a portion of the destination address to locate an entry in the table associated with the portion of the destination address. A pool index is derived from the portion of the destination address and is used to identify a pool of data blocks from among a plurality of pools of data blocks. The entry and the pool of data blocks are navigated to find a next-hop for the packet.
摘要翻译：支持大型互联网协议转发信息库的方法和装置。在网络设备处接收到分组，该分组包括目的地地址。将表索引到使用目标地址的一部分来定位与目标地址的该部分相关联的表中的条目。池索引从目的地地址的部分导出，并且用于从多个数据块池中识别数据块池。数据块的入口和池被导航以找到分组的下一跳。

26. 发明授权

US07480706B1 Multi-threaded round-robin receive for fast network port 有权
标题翻译：多线程循环接收快速网络端口
公开(公告)号：US07480706B1
公开(公告)日：2009-01-20
申请号：US09710496
申请日：2000-11-10
申请人： Donald F. Hooper , Matthew J. Adiletta
发明人： Donald F. Hooper , Matthew J. Adiletta
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L49/90 , H04L47/50 , H04L47/6225 , H04L49/901
摘要： A method of processing network data in a network processor includes assigning a group of receive threads to process network data from a port. Each of the group of receive threads process network data in a round-robin fashion.
摘要翻译：在网络处理器中处理网络数据的方法包括分配一组接收线程以从端口处理网络数据。每组接收线程以循环方式处理网络数据。

27. 发明授权

US07477641B2 Providing access to data shared by packet processing threads 失效
标题翻译：提供对数据包处理线程共享的数据的访问
公开(公告)号：US07477641B2
公开(公告)日：2009-01-13
申请号：US11026652
申请日：2004-12-30
申请人： Sanjeev Jain , Donald F. Hooper
发明人： Sanjeev Jain , Donald F. Hooper
IPC分类号： H04L12/28
CPC分类号： G06F12/0815 , H04L47/50
摘要： In general, in one aspect, the disclosure describes a method that includes at a first packet processing thread executing at a first core, performing a memory read to data shared between packet processing threads including the first thread. The method also includes at the first packet processing thread, determining whether the data returned by the memory read has been changed by a packet processing thread operating on another core before performing an exclusive operation on the shared data by the first packet processing thread.
摘要翻译：通常，一方面，本发明描述了一种方法，其包括在第一核心处执行的第一分组处理线程，对包括第一线程的分组处理线程之间共享的数据执行存储器读取。该方法还包括在第一分组处理线程中，在由第一分组处理线程执行对共享数据的排他操作之前，确定由存储器读取返回的数据是否被在另一核上操作的分组处理线程改变。

28. 发明授权

US07443836B2 Processing a data packet 有权
标题翻译：处理数据包
公开(公告)号：US07443836B2
公开(公告)日：2008-10-28
申请号：US10463217
申请日：2003-06-16
申请人： Donald F. Hooper , Mark B. Rosenbluth , Gilbert Wolrich , Matthew J. Adiletta , Hugh M. Wilkinson, III , Robert J. Kushlis
发明人： Donald F. Hooper , Mark B. Rosenbluth , Gilbert Wolrich , Matthew J. Adiletta , Hugh M. Wilkinson, III , Robert J. Kushlis
IPC分类号： H04L12/66
CPC分类号： G06F9/3851 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9057 , H04L49/9094
摘要： A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.
摘要翻译：描述用于在设备处理数据分组的设备和方法。设备接收数据分组并且确定多个执行线程的一个或多个本地存储器中的可用存储器。该设备将分组信息存储在执行线程的本地存储器中的可用的一个中。

29. 发明授权

US07433307B2 Flow control in a network environment 有权
标题翻译：网络环境中的流量控制
公开(公告)号：US07433307B2
公开(公告)日：2008-10-07
申请号：US10290040
申请日：2002-11-05
申请人： Donald F. Hooper , Myles J. Wilde , Matthew J. Adiletta , Gilbert Wolrich
发明人： Donald F. Hooper , Myles J. Wilde , Matthew J. Adiletta , Gilbert Wolrich
IPC分类号： G01R31/08
CPC分类号： H04L47/263 , H04L12/5601 , H04L47/10 , H04L47/12 , H04L2012/561 , H04L2012/5635 , H04L2012/5636
摘要： Providing flow control includes receiving at a router an indication of the ability of each one of multiple ports not directly connected to the router to receive data from the router and controlling transmission of data from the router to the multiple ports based at least on the indication.
摘要翻译：提供流量控制包括：在路由器处接收指示不直接连接到路由器的多个端口中的每个端口接收来自路由器的数据的能力的指示，并且至少基于指示来控制从路由器到多个端口的数据传输。

30. 发明授权

US06668311B2 Method for memory allocation and management using push/pop apparatus 有权
公开(公告)号：US06668311B2
公开(公告)日：2003-12-23
申请号：US09919058
申请日：2001-07-30
申请人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
发明人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
IPC分类号： G06F1200
CPC分类号： G06F12/023
摘要： An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

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