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    • 22. 发明授权
    • Plasma etch method for forming uniform linewidth residue free patterned composite silicon containing dielectric layer/silicon stack layer
    • 用于形成均匀线宽无残余图案复合硅的电介质层/硅堆叠层的等离子体蚀刻方法
    • US06686292B1
    • 2004-02-03
    • US09221958
    • 1998-12-28
    • Szu-Hung YangSheng-Liang Pan
    • Szu-Hung YangSheng-Liang Pan
    • H01L21311
    • H01L21/308H01L21/3065H01L21/31116H01L21/31144H01L29/66477
    • A method for forming a patterned composite stack layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing dielectric layer. There is then formed upon the blanket silicon containing dielectric layer a patterned photoresist layer. Finally, there is etched sequentially while employing the patterned photoresist layer as a photoresist etch mask the blanket silicon containing dielectric layer and the blanket silicon layer to form a patterned composite stack layer comprising a patterned silicon containing dielectric layer coextensive with a patterned silicon layer, where the sequential etching is undertaken employing in situ in a single plasma reactor chamber or cluster of adjoining chambers a sequential plasma etch method employing a sequence of etching gas compositions which upon plasma activation perform the etching reactions with uniform linewidth dimensions and attenuated polymer residue formation and defect levels.
    • 一种在微电子制造中形成图案化复合叠层的方法。 首先提供基板。 然后在衬底上形成覆盖硅层。 然后在橡皮布硅层上形成覆盖硅的介电层。 然后在覆盖有硅的电介质层上形成图案化的光致抗蚀剂层。 最后,在使用图案化的光致抗蚀剂层作为光刻胶蚀刻掩模,覆盖含硅的介电层和橡皮布硅层以形成图案化复合堆叠层的同时蚀刻顺序地形成图案化复合堆叠层,其包括与图案化的硅层共同延伸的图案化的含硅介电层,其中 在单个等离子体反应器腔室或相邻腔室的阵列中采用原位进行顺序腐蚀,其使用蚀刻气体组合物序列的顺序等离子体蚀刻方法,其在等离子体激活时进行具有均匀线宽尺寸和减弱的聚合物残余物形成和缺陷的蚀刻反应 水平。
    • 24. 发明授权
    • High efficiency color filter process for semiconductor array imaging devices
    • US06274917B1
    • 2001-08-14
    • US09693505
    • 2000-10-23
    • Yang-Tung FanSheng-Liang PanBii-Cheng ChangKuo-Liang Lu
    • Yang-Tung FanSheng-Liang PanBii-Cheng ChangKuo-Liang Lu
    • H01L310232
    • H01L27/14609H01L27/14621H01L27/14627
    • A microelectronic method is described for optimizing the fabrication of optical and semiconductor array structures for high efficiency color image formation in solid-state cameras. Disclosed is an ordered fabrication sequence in which microlens formation precedes color filter layer formation to enable increased image light collection efficiency, to encapsulate and protect the microlens elements from chemical and thermal processing damage, to minimize topographical underlayer variations which would axially misalign or otherwise aberrate microlens elements formed on non-planar surfaces, and, to complete the most difficult steps early in the process to minimize rework and scrap. A CMOS, CID, or CCD optoelectronic configuration is formed by photolithographically patterning a planar-array of photodiodes on a Silicon or other III-V, II-VI, or compound semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, planarized, and, a first convex microlens array of high curvature or other suitable lenses are formed thereon. A transparent encapsulant is deposited to planarize the microlens layer and provide a spacer for the successive deposition(s) of one or more color filter layers. The microlens array may be formed from positive photoresists and the spacer from negative resist, with close attention to matching the index of refraction at layer interfaces. A final surface layer comprising a color filter completes the solid-state color image-forming device.
    • 27. 发明授权
    • Photoresist stripper using nitrogen bubbler
    • 使用氮气鼓泡机的光刻胶剥离器
    • US06911097B1
    • 2005-06-28
    • US09629213
    • 2000-07-31
    • Chie-Chi ChenWen-Hsiang TsengSheng-Liang PanJen-Shiang Fang
    • Chie-Chi ChenWen-Hsiang TsengSheng-Liang PanJen-Shiang Fang
    • B08B3/10B08B5/00H01L21/00
    • H01L21/67086B08B3/102Y10S438/906
    • Provided is a process and apparatus characterized by a gas distribution plate in which a gas supply manifold directs gas bubbles from the bottom of a process tank upward and between wafers contained in a cassette and supported therewithin. This improved method and apparatus is used for effectively stripping photoresist from the larger semiconductor wafers having dense top conductive patterns with protuberant sidewalls. The method provides a scrubbing action that is parallel to the device array being formed on the wafer's surface. Broadly stated, the method of a chemical action on large substrates supported adjacent respective edge portions thereof in a carrier includes submerging the carrier and substrates supported thereby in a process tank containing a liquid chemical, and a gas distribution plate disposed on the bottom of the tank for directing gas bubbles upward and parallel to the surfaces of each substrate contained in the carrier to ensure that a uniform chemical action occurs.
    • 提供了一种工艺和装置,其特征在于气体分配板,其中气体供应歧管将处理罐底部的气泡向上引导到包含在盒中并在其中支撑的晶片之间。 这种改进的方法和装置用于从具有突出侧壁的致密顶部导电图案的较大半导体晶片有效地剥离光致抗蚀剂。 该方法提供了平行于在晶片表面上形成的器件阵列的擦洗动作。 广泛地说,在载体附近支撑在其各个边缘部分上的大的基板上的化学作用的方法包括将载体和由其支撑的基板浸没在包含液体化学品的处理槽中,以及设置在罐的底部上的气体分配板 用于将气泡向上引导并平行于包含在载体中的每个基底的表面,以确保发生均匀的化学作用。
    • 30. 发明授权
    • Wafer rinse tank for metal etching and method for using
    • 用于金属蚀刻的晶圆冲洗槽和使用方法
    • US06360756B1
    • 2002-03-26
    • US09325307
    • 1999-06-03
    • Chie-Chi ChenTzu-Yang ChungSzu-Yao WangSheng-Liang Pan
    • Chie-Chi ChenTzu-Yang ChungSzu-Yao WangSheng-Liang Pan
    • B08B704
    • H01L21/67057B08B3/102Y10S134/902
    • A rinse tank for rinsing electronic substrates after a chemical process and a method for utilizing such rinse tank are provided. In the rinse tank, devices for performing a quick dump rinse; for performing a cascade overflow rinse and for feeding an inert gas bubbling are provided in the cavity of a single rinse tank. By utilizing the present invention novel rinse tank, the processing problems frequently observed in conventional rinse tanks where two rinse tanks are required for the quick dump rinse and for the cascade overflow rinse, such as particle re-deposition and a large floor space area requirement are eliminated. Furthermore, the wafer rinse process after a metal etching process can be accomplished in a total process time that is at least 2˜3 minutes shorter than that required by using conventional rinse tanks.
    • 提供了一种用于在化学过程之后冲洗电子基板的冲洗槽和用于使用这种冲洗槽的方法。 在冲洗槽中,进行快速冲洗冲洗的装置; 在单个冲洗槽的空腔中设置用于进行级联溢流冲洗和用于进料惰性气体鼓泡的装置。 通过利用本发明的新型漂洗槽,在常规冲洗槽中经常观察到的处理问题,其中需要两个漂洗槽用于快速冲洗冲洗和级联溢流冲洗,例如颗粒再沉积和大的占地空间面积要求, 消除了 此外,在金属蚀刻工艺之后的晶片冲洗过程可以在比使用常规冲洗槽所需的总处理时间短至少2〜3分钟的时间内完成。