专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050250345A1 METHOD FOR FABRICATING A BOTTLE-SHAPED DEEP TRENCH 审中-公开
标题翻译：用于制造瓶形深层TRENCH的方法
公开(公告)号：US20050250345A1
公开(公告)日：2005-11-10
申请号：US10709444
申请日：2004-05-06
申请人： Chien-Jung Sun , Chang-Rong Wu
发明人： Chien-Jung Sun , Chang-Rong Wu
IPC分类号： H01L21/302 , H01L21/308 , H01L21/31 , H01L21/334 , H01L21/461 , H01L21/469 , H01L21/76 , H01L21/8242
CPC分类号： H01L21/3083 , H01L27/1087 , H01L29/66181
摘要： A method for fabricating a bottle-shaped deep trench. The method comprises providing a substrate having a pad layer thereon, etching the pad layer and the substrate to form a deep trench in the substrate, performing an ALD process to form a nonmetal layer on the pad layer and on an upper portion of the sidewall of the deep trench, and performing an isotropic etching process to the sidewall and the bottom surface of the deep trench by taking the nonmetal layer as a hard mask so as to form a bottle-shaped deep trench.
摘要翻译：一种制造瓶形深沟槽的方法。该方法包括提供其上具有衬垫层的衬底，蚀刻衬垫层和衬底以在衬底中形成深沟槽，执行ALD工艺以在焊盘层和侧壁的上部形成非金属层通过将非金属层作为硬掩模进行深沟槽的侧壁和底表面的各向同性蚀刻处理，以形成瓶形深沟槽。

22. 发明授权

US06960530B2 Method of reducing the aspect ratio of a trench 有权
标题翻译：降低沟槽纵横比的方法
公开(公告)号：US06960530B2
公开(公告)日：2005-11-01
申请号：US10724435
申请日：2003-11-28
申请人： Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu , Hung-Chang Liao
发明人： Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu , Hung-Chang Liao
IPC分类号： H01L21/311 , H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76224 , H01L21/31116 , H01L21/31612
摘要： A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.
摘要翻译：减小沟槽纵横比的方法。在衬底中形成沟槽。通过HDPCVD在沟槽的表面上形成共形的富Si氧化物层。通过HDPCVD在富Si氧化物层上形成保形第一氧化物层。通过LPCVD在第一氧化物层上形成保形的第二氧化物层。通过各向异性蚀刻去除部分富Si氧化物层，第二氧化物层和第一氧化物层，以形成由剩余的富Si氧化物层，剩余的第二氧化物层和剩余的第一氧化物层组成的氧化物间隔物。剩余的第二氧化物层，剩余的第一氧化物层的一部分和富Si氧化物层的一部分被BOE除去。因此，剩余的第一和富Si氧化物层的一部分形成在沟槽的下表面上，从而减小沟槽纵横比。

23. 发明申请

US20050124127A1 Method for manufacturing gate structure for use in semiconductor device 审中-公开
标题翻译：制造用于半导体器件的栅极结构的方法
公开(公告)号：US20050124127A1
公开(公告)日：2005-06-09
申请号：US10726500
申请日：2003-12-04
申请人： Tzu-En Ho , Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu
发明人： Tzu-En Ho , Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/4763 , H01L29/49 , H01L29/51
CPC分类号： H01L29/4933 , H01L21/28052 , H01L29/51 , H01L29/517 , H01L29/518
摘要： The present invention provides a method for manufacturing a stacked gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer, and a tungsten layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.
摘要翻译：本发明提供一种在半导体器件中制造堆叠栅极结构的方法。该方法包括以下步骤：在半导体衬底上依次形成栅极电介质层，多晶硅层，金属层，势垒层和钨层，在氮气环境中进行快速热退火（RTA）在所述钨层上形成氮化硅层，并将所述多层薄膜结构图案化为规定的形态。

24. 发明申请

US20050074957A1 Methods for manufacturing stacked gate structure and field effect transistor povided with the same 有权
标题翻译：堆叠栅极结构和场效应晶体管的制造方法相同
公开(公告)号：US20050074957A1
公开(公告)日：2005-04-07
申请号：US10864320
申请日：2004-06-10
申请人： Tzu-En Ho , Chang-Rong Wu
发明人： Tzu-En Ho , Chang-Rong Wu
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28061 , H01L29/4933
摘要： The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.
摘要翻译：本发明提供一种在半导体器件中制造堆叠栅极结构的方法。该方法包括以下步骤：在半导体衬底上依次形成栅介质层，多晶硅层，钛层和WNX层，在氮气环境中进行快速热退火（RTA），形成氮化硅层，并且将多层薄膜结构图案化成预定的构造。

25. 发明授权

US07375017B2 Method for fabricating semiconductor device having stacked-gate structure 有权
标题翻译：具有层叠栅结构的半导体器件的制造方法
公开(公告)号：US07375017B2
公开(公告)日：2008-05-20
申请号：US11338579
申请日：2006-01-23
申请人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
发明人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
IPC分类号： H01L21/3205
CPC分类号： H01L21/28052 , H01L29/4933
摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.
摘要翻译：一种半导体制造方法，该半导体器件具有堆叠栅极结构。通过介电层与衬底绝缘的衬底上形成多晶硅层。在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。使用氮气和氢气对氮化钨层进行退火。依次形成覆盖氮化钨层的钨层和覆盖层。

26. 发明授权

US07232718B2 Method for forming a deep trench capacitor buried plate 有权
标题翻译：形成深沟槽电容器掩埋板的方法
公开(公告)号：US07232718B2
公开(公告)日：2007-06-19
申请号：US10605234
申请日：2003-09-17
申请人： Chih-Han Chang , Hsin-Jung Ho , Chang-Rong Wu , Chien-Jung Sun
发明人： Chih-Han Chang , Hsin-Jung Ho , Chang-Rong Wu , Chien-Jung Sun
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited in the deep trench, and etched back to expose parts of the doped silicate film. Then, an etching process is performed to remove the exposed doped silicate film and parts of the pad oxide for forming a recess. The sacrificial layer is removed. A silicon nitride layer is deposited to fill the recess and to cover the doped silicate film. Finally, a thermal oxidation process is performed to form a doped ion region. The silicon nitride layer is removed. The doped silicate film is removed.
摘要翻译：一种形成深沟槽电容器掩埋板的方法。提供具有衬垫氧化物和衬垫氮化物的衬底。在衬底中形成深沟槽。掺杂的硅酸盐膜沉积在深沟槽的侧壁上。牺牲层沉积在深沟槽中，并被回蚀以暴露部分掺杂的硅酸盐膜。然后，进行蚀刻处理以去除暴露的掺杂硅酸盐膜和用于形成凹槽的衬垫氧化物的一部分。牺牲层被去除。沉积氮化硅层以填充凹部并覆盖掺杂的硅酸盐膜。最后，进行热氧化工艺以形成掺杂的离子区域。去除氮化硅层。去除掺杂的硅酸盐膜。

27. 发明授权

US07154159B2 Trench isolation structure and method of forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US07154159B2
公开(公告)日：2006-12-26
申请号：US10784203
申请日：2004-02-24
申请人： Chien-Chang Cheng , Shing-Yih Shih , Chang-Rong Wu
发明人： Chien-Chang Cheng , Shing-Yih Shih , Chang-Rong Wu
IPC分类号： H01L29/00
CPC分类号： H01L21/76224
摘要： A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the trench. A dielectric layer, such as spin-on glass, is formed in the trench upon the polysilicon liner.
摘要翻译：提供了沟槽隔离结构和形成沟槽隔离结构的方法。该方法包括提供具有沟槽的衬底。在沟槽中形成多晶硅衬垫。在多晶硅衬垫上的沟槽中形成介电层，例如旋涂玻璃。

28. 发明授权

US07138338B2 Method and composite hard mask for forming deep trenches in a semiconductor substrate 有权
标题翻译：用于在半导体衬底中形成深沟槽的方法和复合硬掩模
公开(公告)号：US07138338B2
公开(公告)日：2006-11-21
申请号：US10810804
申请日：2004-03-29
申请人： Chang-Rong Wu , Yinan Chen , Tuz-Ching Tsai
发明人： Chang-Rong Wu , Yinan Chen , Tuz-Ching Tsai
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/0332 , H01L21/76224 , H01L29/66181
摘要： A method and structure for forming deep trenches in a semiconductor substrate is provided. The method comprises: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a pad nitride layer on the pad oxide layer; forming a borophosphosilicate glass layer on the pad nitride layer; forming a borosilicate glass layer on the borophosphosilicate glass layer; and forming deep trenches through the borosilicate glass layer, through the borophosphosilicate glass layer, through the pad nitride, through the pad oxide, and into the semiconductor substrate. The borosilicate glass layer and the borophosphosilicate glass layer function as a composite hard mask in forming the deep trenches. With the borophosphosilicate glass layer, the composite hard mask can be easily removed by dry etch process using hydrogen fluoride vapor after the deep trenches have been formed.
摘要翻译：提供了一种在半导体衬底中形成深沟槽的方法和结构。该方法包括：提供半导体衬底; 在所述半导体衬底上形成衬垫氧化物层; 在所述焊盘氧化物层上形成衬垫氮化物层; 在衬垫氮化物层上形成硼磷硅酸盐玻璃层; 在硼磷硅酸盐玻璃层上形成硼硅酸盐玻璃层; 并通过硼硅酸盐玻璃层，通过硼磷硅酸盐玻璃层，通过衬垫氮化物，通过衬垫氧化物形成深沟槽并进入半导体衬底。硼硅酸盐玻璃层和硼磷硅酸盐玻璃层在形成深沟槽时用作复合硬掩模。对于硼磷硅酸盐玻璃层，在形成深沟槽之后，可以通过使用氟化氢蒸气的干法蚀刻工艺容易地去除复合硬掩模。

29. 发明申请

US20050020028A1 Method for fabricating trench isolation 有权
标题翻译：沟槽隔离方法
公开(公告)号：US20050020028A1
公开(公告)日：2005-01-27
申请号：US10690859
申请日：2003-10-22
申请人： Chien-Mao Liao , Tzu-En Ho , Chang-Rong Wu , Chih-How Chang , Sheng-Wei Yang , Sheng-Tsung Chen , Chung-Yuan Lee , Wen-Sheng Liao , Chen-Chou Huang
发明人： Chien-Mao Liao , Tzu-En Ho , Chang-Rong Wu , Chih-How Chang , Sheng-Wei Yang , Sheng-Tsung Chen , Chung-Yuan Lee , Wen-Sheng Liao , Chen-Chou Huang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.
摘要翻译：一种形成沟槽隔离的方法。提供具有开口的半导体衬底，其上形成有掩模层。在半导体衬底和沟槽上顺应地形成第一绝缘层，并且沟槽被第一绝缘层填充。将第一绝缘层各向异性地蚀刻到半导体衬底的下面。在半导体衬底和沟槽上形成第二绝缘层。将第二绝缘层平坦化以露出掩模层。

30. 发明授权

US07101777B2 Methods for manufacturing stacked gate structure and field effect transistor provided with the same 有权
标题翻译：制造堆叠栅极结构的方法和具有该栅极结构的场效应晶体管
公开(公告)号：US07101777B2
公开(公告)日：2006-09-05
申请号：US10864320
申请日：2004-06-10
申请人： Tzu-En Ho , Chang-Rong Wu
发明人： Tzu-En Ho , Chang-Rong Wu
IPC分类号： H01L21/3205
CPC分类号： H01L29/7833 , H01L21/28061 , H01L29/4933
摘要： The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.
摘要翻译：本发明提供一种在半导体器件中制造堆叠栅极结构的方法。该方法包括以下步骤：在半导体衬底上顺序地形成栅介质层，多晶硅层，钛层和WN层，并进行快速热退火（RTA）氮气环境，在钨层上形成氮化硅层，并将多层薄膜结构图案化成预定的构型。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式