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21. 发明授权

US06687895B2 Method and apparatus for reducing optical proximity correction output file size 有权
标题翻译：降低光学接近校正输出文件大小的方法和装置
公开(公告)号：US06687895B2
公开(公告)日：2004-02-03
申请号：US10189900
申请日：2002-07-03
申请人： Youping Zhang
发明人： Youping Zhang
IPC分类号： G06F1750
CPC分类号： G03F1/36
摘要： An approach to reducing the size of an output file generated by an optical proximity correction (OPC) process is described. An OPC output can be examined to identify identically sized segments with identical biases. Adjoining segments to those first identified to identify repeating basic shapes. Those basic shapes can be further refined and expanded as desired. Finally, the output is rewritten making use of the repeating shapes in a hierarchical output that places each shape once as a child cell of the original geometry and uses references to that shape in other locations thereby reducing data volume size. The data volume savings can be considerable.
摘要翻译：描述了通过光学邻近校正（OPC）过程生成的减小输出文件的大小的方法。可以检查OPC输出以识别具有相同偏差的相同大小的段。将第一段识别为识别重复基本形状的段相邻。这些基本形状可以根据需要进一步细化和扩展。最后，输出被重写，使用层次输出中的重复形状，将每个形状一次作为原始几何的子单元，并在其他位置使用对该形状的引用，从而减少数据量大小。数据量的节省可以很大。

22. 发明授权

US07934184B2 Integrated circuit design using modified cells 有权
标题翻译：集成电路设计采用修改单元格
公开(公告)号：US07934184B2
公开(公告)日：2011-04-26
申请号：US11273685
申请日：2005-11-14
申请人： Youping Zhang
发明人： Youping Zhang
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068
摘要： An exemplary method for modifying at least part of an integrated circuit layout comprises obtaining an integrated circuit device layout, the integrated circuit device being designed using a library of cells, obtaining a modified library of cells, and replacing at least one cell in the integrated circuit device layout with a corresponding modified cell of the modified library to obtain a modified integrated circuit device layout. The modified library includes modified cells corresponding to cells in the library and candidate areas of each modified cell indicating portions of the cell for further processing. At least some of the modified cells have been modified to at least partially compensate for a manufacturing effect.
摘要翻译：用于修改集成电路布局的至少一部分的示例性方法包括获得集成电路器件布局，使用单元库设计的集成电路器件，获得修改的单元库，以及替换集成电路中的至少一个单元设备布局与修改库的相应修改单元获得修改后的集成电路设备布局。修饰的文库包括对应于文库中的细胞的修饰细胞和每个修饰的细胞的候选区域，指示细胞的部分用于进一步处理。修饰的细胞中的至少一些已被修饰以至少部分补偿制造效果。

23. 发明申请

US20100153904A1 Model-based pattern characterization to generate rules for rule-model-based hybrid optical proximity correction 有权
标题翻译：基于模型的模式表征，以生成基于规则模型的混合光学邻近校正规则
公开(公告)号：US20100153904A1
公开(公告)日：2010-06-17
申请号：US12592674
申请日：2009-12-01
申请人： Youping Zhang
发明人： Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F1/36 , G03F7/70441
摘要： A system and method are provided for analyzing layout patterns via simulation using a lithography model to characterize the patterns and generate rules to be used in rule-based optical proximity correction (OPC). The system and method analyze a series of layout patterns conforming to a set of design rules by simulation using a lithography model to obtain a partition of the pattern spaces into one portion that requires only rule-based OPC and another portion that requires model-based OPC. A corresponding hybrid OPC system and method are also introduced that utilize the generated rules to correct an integrated circuit (IC) design layout which reduces the OPC output complexity and improves turnaround time.
摘要翻译：提供了一种系统和方法，用于通过使用光刻模型的模拟来分析布局图案，以表征图案并生成将用于基于规则的光学邻近校正（OPC）中的规则。该系统和方法通过使用光刻模型进行模拟分析符合一组设计规则的一系列布局模式，以将模式空间的分区获得到仅需要基于规则的OPC的部分，并且需要基于模型的OPC的另一部分。还引入了一种相应的混合OPC系统和方法，利用生成的规则来校正集成电路（IC）设计布局，降低了OPC输出的复杂度并改善了周转时间。

24. 发明申请

US20090241087A1 System for simplifying layout processing 有权
公开(公告)号：US20090241087A1
公开(公告)日：2009-09-24
申请号：US12322489
申请日：2009-02-02
申请人： Youping Zhang , Weinong Lai
发明人： Youping Zhang , Weinong Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

25. 发明授权

US07523429B2 System for designing integrated circuits with enhanced manufacturability 失效
标题翻译：具有增强可制造性的集成电路设计系统
公开(公告)号：US07523429B2
公开(公告)日：2009-04-21
申请号：US11060927
申请日：2005-02-18
申请人： Armen Kroyan , Youping Zhang , Etsuya Morita , Adrianus Ligtenberg
发明人： Armen Kroyan , Youping Zhang , Etsuya Morita , Adrianus Ligtenberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.
摘要翻译：公开了用于集成电路设计的系统和方法，以通过生成捕获局部布局要求的分级设计规则来提高电路布局的可制造性。与采用全球设计规则的常规技术相比，本文所公开的IC设计系统和方法基于指定的布局和集成电路特性将原始设计布局分割成所需的粒度级别。在本地化的层面上，适当地调整设计规则以从可制造性的角度捕获关键方面。然后将这些调整后的设计规则用于执行本地化的布局操作和掩码数据转换。

26. 发明授权

US08782574B2 System for simplifying layout processing 有权
标题翻译：用于简化布局处理的系统
公开(公告)号：US08782574B2
公开(公告)日：2014-07-15
申请号：US12322489
申请日：2009-02-02
申请人： Youping Zhang , Weinong Lai
发明人： Youping Zhang , Weinong Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.
摘要翻译：公开了用于集成电路设计的系统和方法，以通过应用布局处理来处理诸如集成电路设计布局中的点动的缺陷来增强电路布局的可制造性。布局处理可以应用于原始集成电路设计布局中的点动或者通过过程偏差创建的后设计，以及设计规则检查和布尔过程或过程补偿。

27. 发明申请

US20130014065A1 Methods and Systems for Pattern Design with Tailored Response to Wavefront Aberration 有权
标题翻译：用于波前像差定向响应的图案设计方法与系统
公开(公告)号：US20130014065A1
公开(公告)日：2013-01-10
申请号：US13542625
申请日：2012-07-05
申请人： Hanying Feng , Yu Cao , Jun Ye , Youping Zhang
发明人： Hanying Feng , Yu Cao , Jun Ye , Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F7/706 , G03F7/70683
摘要： The present invention relates to methods and systems for designing gauge patterns that are extremely sensitive to parameter variation, and thus robust against random and repetitive measurement errors in calibration of a lithographic process utilized to image a target design having a plurality of features. The method may include identifying most sensitive line width/pitch combination with optimal assist feature placement which leads to most sensitive CD (or other lithography response parameter) changes against lithography process parameter variations, such as wavefront aberration parameter variation. The method may also include designing gauges which have more than one test patterns, such that a combined response of the gauge can be tailored to generate a certain response to wavefront-related or other lithographic process parameters. The sensitivity against parameter variation leads to robust performance against random measurement error and/or any other measurement error.
摘要翻译：本发明涉及用于设计对参数变化非常敏感的规格图案的方法和系统，因此对于用于对具有多个特征进行成像的目标设计的光刻工艺的校准中的随机和重复的测量误差是鲁棒的。该方法可以包括以最佳辅助特征放置来识别最敏感的线宽/间距组合，其导致针对光刻过程参数变化（例如波前像差参数变化）的最敏感的CD（或其他光刻响应参数）变化。该方法还可以包括设计具有多于一个测试图案的计量器，使得量规的组合响应可以被调整以产生对波前相关或其它光刻工艺参数的特定响应。对参数变化的敏感性导致对随机测量误差和/或任何其他测量误差的鲁棒性能。

28. 发明申请

US20120216156A1 Method of Pattern Selection for Source and Mask Optimization 有权
标题翻译：源和掩码优化的模式选择方法
公开(公告)号：US20120216156A1
公开(公告)日：2012-08-23
申请号：US13505286
申请日：2010-10-26
申请人： Hua-Yu Liu , Luoqi Chen , Hong Chen , Zhi-Pan Li , Jun Ye , Min-Chun Tsai , Youping Zhang , Yen-Wen Lu , Jiangwei Li
发明人： Hua-Yu Liu , Luoqi Chen , Hong Chen , Zhi-Pan Li , Jun Ye , Min-Chun Tsai , Youping Zhang , Yen-Wen Lu , Jiangwei Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/144 , G03F1/36 , G03F7/70125 , G03F7/70425 , G03F7/70441 , G03F7/705 , G03F7/70666 , G06F17/50 , G06F17/5009
摘要： The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.
摘要翻译：本发明涉及从设计中选择模式子集的方法，以及执行源和掩码优化的方法以及用于执行从设计中选择模式子集的方法的计算机程序产品。根据某些方面，本发明能够覆盖整个设计，同时降低计算成本，通过智能地从设计中选择图案子集，其中设计的设计或修改被配置为经由光刻成像到衬底上处理。从设计中选择图案子集的方法包括从与设计的预定义表示相关的设计中识别一组图案。通过根据该方法选择模式子集，所选择的模式子集构成与模式集合相似的设计表示。

29. 发明授权

US07487490B2 System for simplifying layout processing 有权
标题翻译：用于简化布局处理的系统
公开(公告)号：US07487490B2
公开(公告)日：2009-02-03
申请号：US11091067
申请日：2005-03-28
申请人： Youping Zhang , Weinong Lai
发明人： Youping Zhang , Weinong Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.
摘要翻译：公开了用于集成电路设计的系统和方法，以通过应用布局处理来处理诸如集成电路设计布局中的点动的缺陷来增强电路布局的可制造性。布局处理可以应用于原始集成电路设计布局中的点动或者通过过程偏差创建的后设计，以及设计规则检查和布尔过程或过程补偿。

30. 发明申请

US20080201686A1 METHOD AND APPARATUS FOR PERFORMING TARGET-IMAGE-BASED OPTICAL PROXIMITY CORRECTION 有权
标题翻译：用于实现目标图像的光学近似校正的方法和装置
公开(公告)号：US20080201686A1
公开(公告)日：2008-08-21
申请号：US12112908
申请日：2008-04-30
申请人： Youping Zhang
发明人： Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F9/00 , G03F1/30 , G03F1/36 , G03F1/70
摘要： A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes a target image for a target feature defined by the plurality of masks, wherein mask features from different masks define the target image. The system dissects the feature into a plurality of segments, wherein dissecting the mask feature involves using dissection parameters associated with geometric characteristics of the target image, instead of using dissection parameters associated with geometric characteristics of the mask feature. The system then performs an optical proximity correction (OPC) operation on the plurality of masks, wherein the OPC operation uses parameters associated with geometric characteristics of the target image to perform optical proximity correction on the mask features that define the target image.
摘要翻译：提出了一种在用于生成集成电路的掩模上执行基于目标图像的光学邻近校正的系统。该系统首先接收用于暴露集成电路上的特征的多个掩模来操作。接下来，系统计算由多个掩模定义的目标特征的目标图像，其中来自不同掩模的掩模特征定义目标图像。该系统将特征解剖成多个段，其中解剖掩模特征涉及使用与目标图像的几何特征相关联的解剖参数，而不是使用与掩模特征的几何特征相关联的解剖参数。然后，系统对多个掩模执行光学邻近校正（OPC）操作，其中OPC操作使用与目标图像的几何特征相关联的参数来对限定目标图像的掩模特征进行光学邻近校正。

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