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21. 发明申请

US20110193230A1 FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES 失效
标题翻译：形成有保护金属线的空气隙
公开(公告)号：US20110193230A1
公开(公告)日：2011-08-11
申请号：US12700792
申请日：2010-02-05
申请人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
发明人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L24/80 , H01L21/0337 , H01L21/31144 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L23/53295
摘要： A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.
摘要翻译：提供了一种用于制造其电介质层中具有气隙的微电子元件的方法。可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层的表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并且延伸第二高度电介质层的表面的高度，第二高度大于第一高度。在形成盖层之后，可以在盖层之上形成掩模。掩模可以具有多个随机布置的孔。每个孔可以暴露仅具有较大高度的盖层的第二部分的表面。掩模可以完全覆盖具有较低高度的盖层的第一部分的表面。随后，可以将蚀刻剂引导到盖层的第一和第二部分，以在盖层中形成与掩模中的孔对准的孔。可以通过盖层中的孔从暴露于蚀刻剂的介电层去除材料。此时，掩模可以保护盖层的第一部分和金属线不被蚀刻剂侵蚀。

22. 发明授权

US07687877B2 Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same 有权
标题翻译：具有蘑菇状氧化物覆盖层的互连结构及其制造方法
公开(公告)号：US07687877B2
公开(公告)日：2010-03-30
申请号：US12115944
申请日：2008-05-06
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality of conductive features 56. A first dielectric cap 58 is located on the upper surface of the dielectric material 52′ and extends onto at least a portion of the upper surface of each of the plurality of conductive features 56. As shown, the first dielectric cap 58 forms an interface 59 with each of the plurality of conductive features 56 that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap 60 located on an exposed portion of the upper surface of each of the plurality of conductive features 56 not covered with the first dielectric cap 58. The second dielectric cap 60 further covers on an exposed surface of the first dielectric cap 58.
摘要翻译：提供一种互连结构，其包括介电常数为4.0或更小的介电材料52'，并且包括嵌入其中的多个导电特征56。电介质材料52'具有位于多个导电特征56中的每一个的上表面下方的上表面52r。第一电介质盖58位于电介质材料52'的上表面上并延伸至至少一个多个导电特征56中的每一个的上表面的一部分。如图所示，第一电介质盖58形成接口59，多个导电特征56中的每一个与由相邻导电特征。本发明的结构还包括位于多个导电特征56的每一个的上表面的未被第一电介质盖58覆盖的暴露部分上的第二电介质帽60.第二电介质帽60还覆盖在第一电介质盖58。

23. 发明申请

US20090184400A1 VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE 有权
标题翻译：通过采用方法和相关半导体结构
公开(公告)号：US20090184400A1
公开(公告)日：2009-07-23
申请号：US12017141
申请日：2008-01-21
申请人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Steven J. Holmes , David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/311 , H01L23/538
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.
摘要翻译：公开了通孔沟槽的方法和相关的半导体结构。在一个实施例中，该方法包括在电介质材料中形成通孔，通孔与导体对准; 在介电材料和通孔开口上形成保护涂层; 通过刨花进行; 并且在电介质材料的水平表面上去除保护涂层。半导体结构可以包括与导体具有界面的通孔，所述界面包括延伸到导体表面中并经过导体表面的三维成形区域，其中三维成形区域的外边缘与最外表面的通道。

24. 发明申请

US20140061930A1 OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE 有权
标题翻译：通过掩蔽和反应离子蚀刻（RIE）技术的超耐性
公开(公告)号：US20140061930A1
公开(公告)日：2014-03-06
申请号：US13604660
申请日：2012-09-06
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
摘要翻译：提供了一种方法，其包括首先根据第一掩模蚀刻衬底。第一蚀刻在衬底中形成第一深度的第一蚀刻特征。第一蚀刻还在衬底中形成条条开口。然后可以用填充材料填充条子开口。可以通过去除第一掩模的一部分来形成第二掩模。可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

25. 发明授权

US08609534B2 Electrical fuse structure and method of fabricating same 有权
标题翻译：电熔丝结构及其制造方法
公开(公告)号：US08609534B2
公开(公告)日：2013-12-17
申请号：US12890941
申请日：2010-09-27
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H01L21/4763
CPC分类号： H01L23/5256 , H01L21/76805 , H01L21/76807 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.
摘要翻译：使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。通孔开口位于顶部并连接到金属层。双镶嵌结构还包括线路开口和通孔开口内的导电特征。电介质间隔物也存在于线路开口和通孔开口内。介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。因此，提供了节省空间的高编程效率电熔丝。

26. 发明申请

US20130328208A1 DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME 有权
标题翻译：双重对等双向对联方案
公开(公告)号：US20130328208A1
公开(公告)日：2013-12-12
申请号：US13490542
申请日：2012-06-07
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76819 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
摘要翻译：在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。之后形成第二电介质材料层。在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的第一条金属线。形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

27. 发明申请

US20130320411A1 BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION 审中-公开
公开(公告)号：US20130320411A1
公开(公告)日：2013-12-05
申请号：US13488581
申请日：2012-06-05
申请人： Su-Chen Fan , Balasubramanian S. Haran , David V. Horak , Shom Ponoth , Chih-Chao Yang
发明人： Su-Chen Fan , Balasubramanian S. Haran , David V. Horak , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/76834 , H01L21/76897 , H01L29/66545
摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.

28. 发明授权

US08492270B2 Structure for nano-scale metallization and method for fabricating same 有权
标题翻译：纳米级金属化结构及其制造方法
公开(公告)号：US08492270B2
公开(公告)日：2013-07-23
申请号：US12885665
申请日：2010-09-20
申请人： Shom Ponoth , David V Horak , Elbert E Huang , Sivananda K Kanakasabapathy , Charles W Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V Horak , Elbert E Huang , Sivananda K Kanakasabapathy , Charles W Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53266 , H01L21/32139 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.
摘要翻译：为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

29. 发明申请

US20130112462A1 Metal Alloy Cap Integration 审中-公开
标题翻译：金属合金盖整合
公开(公告)号：US20130112462A1
公开(公告)日：2013-05-09
申请号：US13290557
申请日：2011-11-07
申请人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Charles W. Koburger, III , Shom Ponoth
IPC分类号： H05K1/09 , H05K3/00
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76849 , H01L21/76877 , H01L21/76882 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T29/49124 , H01L2924/00
摘要： A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer.
摘要翻译：包括金属合金覆盖层的金属互连结构及其制造方法。互连特征内的原始沉积的合金覆盖层元件将扩散到并分离到金属互连的顶表面上。金属合金覆盖材料沉积在回流铜表面上，并且不物理地与互连特征的侧壁接触。因此，互连结构中的残余合金元素的电阻率冲击降低。也就是说，在金属互连结构的特征内部存在合金元素的减少。金属互连结构包括具有凹陷线的介电层，侧壁上的衬垫材料，铜材料，合金盖和覆盖层。

30. 发明授权

US08404582B2 Structure and method for manufacturing interconnect structures having self-aligned dielectric caps 有权
标题翻译：用于制造具有自对准电介质盖的互连结构的结构和方法
公开(公告)号：US08404582B2
公开(公告)日：2013-03-26
申请号：US12773306
申请日：2010-05-04
申请人： David V Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.
摘要翻译：提供具有自对准电介质盖的互连结构。在基板上形成至少一个金属化层。电介质盖被选择性地沉积在金属化层上。

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