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21. 发明申请

US20080224119A1 PHASE CHANGE MEMORY ELEMENT AND METHOD OF MAKING THE SAME 失效
标题翻译：相变记忆元件及其制造方法
公开(公告)号：US20080224119A1
公开(公告)日：2008-09-18
申请号：US12130075
申请日：2008-05-30
申请人： Geoffrey W. Burr , Yi-Chou Chen , Hsiang-Lan Lung
发明人： Geoffrey W. Burr , Yi-Chou Chen , Hsiang-Lan Lung
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/122 , G11C13/0004 , G11C2213/55 , H01L45/06 , H01L45/1675
摘要： Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.
摘要翻译：具有通过重叠薄膜形成的具有小的相变开关体积的薄膜相变存储器。示例性实施例包括相变存储元件，包括具有电阻的第一相变层，具有电阻的第二相变层，设置在第一和第二相变层之间的绝缘层; 以及具有电阻的第三相变层，并且耦合到所述第一和第二相变层中的每一个，桥接所述绝缘层并电耦合所述第一和第二相变层，其中所述第三相变层的电阻大于第一相变层和第二相变层的电阻。

22. 发明申请

US20060110878A1 Side wall active pin memory and manufacturing method 有权
公开(公告)号：US20060110878A1
公开(公告)日：2006-05-25
申请号：US11285473
申请日：2005-11-21
申请人： Hsiang Lung , Shih-Hung Chen , Yi-Chou Chen
发明人： Hsiang Lung , Shih-Hung Chen , Yi-Chou Chen
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/302
CPC分类号： H01L27/112 , G11C2213/52 , H01L21/0337 , H01L21/0338 , H01L27/115 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/124 , H01L45/144 , H01L45/1691
摘要： A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is about 40 nanometers or less.

23. 发明授权

US06828081B2 Method and system for lithography using phase-change material 有权
公开(公告)号：US06828081B2
公开(公告)日：2004-12-07
申请号：US10315003
申请日：2002-12-10
申请人： Yi-Chou Chen , Chih-Yuan Lu , Hsiang-Lan Lung , Li-Hsin Chuang
发明人： Yi-Chou Chen , Chih-Yuan Lu , Hsiang-Lan Lung , Li-Hsin Chuang
IPC分类号： H01L2182
CPC分类号： H01L45/1213 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Methods and systems are provided for forming an electrical interconnect layer between two layers of an integrated circuit. The interconnect layer is formed using a material having a first electrical conductivity corresponding to a first state and a second electrical conductivity corresponding to a second state, where the first electrical conductivity is different from the second electrical conductivity. An area of the material of the interconnect layer may be selected, for example, using a mask. Then energy may be applied to the selected area to change the electrical conductivity of the material in the selected area of the interconnect layer. Thus, the present invention may be used to implement optical memory devices which may be read by an electrical circuit.

24. 发明授权

US08946671B2 Mask read only memory containing diodes and method of manufacturing the same 有权
标题翻译：掩模只读存储器二极管及其制造方法
公开(公告)号：US08946671B2
公开(公告)日：2015-02-03
申请号：US10642244
申请日：2003-08-18
申请人： Sheng-Chih Lai , Hsiang-Lan Lung , Yi-Chou Chen
发明人： Sheng-Chih Lai , Hsiang-Lan Lung , Yi-Chou Chen
IPC分类号： H01L47/00 , H01L27/102 , H01L21/822 , H01L27/06
CPC分类号： H01L27/1021 , H01L21/8221 , H01L27/0688
摘要： A mask read only memory containing diodes and method of manufacturing the same. The mask read only memory is a high-density three dimensional array formed by stacking a plurality of diode layers and the logic “0” or “1” is defined by whether there is a dielectric layer on the diode.
摘要翻译：掩模只读存储器二极管及其制造方法。掩模只读存储器是通过堆叠多个二极管层形成的高密度三维阵列，并且逻辑“0”或“1”由二极管上是否存在介电层来定义。

25. 发明授权

US08295075B2 Resistive memory and method for controlling operations of the same 有权
标题翻译：电阻记忆及其控制方法
公开(公告)号：US08295075B2
公开(公告)日：2012-10-23
申请号：US12753316
申请日：2010-04-02
申请人： Wei-Chih Chien , Yi-Chou Chen , Feng-Ming Lee
发明人： Wei-Chih Chien , Yi-Chou Chen , Feng-Ming Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/51 , G11C2213/71 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146
摘要： A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.
摘要翻译：提供了一种用于控制电阻性存储器的操作的电阻性存储器和方法。电阻性存储器具有第一存储器层，第二存储器层和介质层。第一存储器层和第二存储器层中的每一个用于存储数据。介质层形成在第一存储层和第二存储层之间。该方法至少包括测量第一存储层和第二存储层之间的电阻的步骤，以及根据测得的电阻确定第一状态，第二状态和第三状态中的哪一种是电阻性存储器的状态。

26. 发明授权

US08180942B2 Arbitration device and method 有权
标题翻译：仲裁设备及方法
公开(公告)号：US08180942B2
公开(公告)日：2012-05-15
申请号：US12358975
申请日：2009-01-23
申请人： Yi-Chou Chen
发明人： Yi-Chou Chen
IPC分类号： G06F13/14 , G09G5/39 , G09G5/36 , G09G5/00
CPC分类号： G09G5/001 , G09G5/14 , G09G2360/06
摘要： An arbitration device receives a plurality of requests from a plurality of circuits, and grants access to one of the plurality of circuits. The arbitration device includes a sorter and an arbitrator. The sorter receives position information of an image signal including a plurality of image layers, and determines an access priority including a first group and a second group according to the position information. The arbitrator receives the access priority and at least one of the plurality of requests, and grants the access to one of the plurality of circuits according to the access priority and the at least one of the plurality of requests. In addition, each of the plurality of circuits generates data for each of the image layers correspondingly.
摘要翻译：仲裁装置从多个电路接收多个请求，并且允许对多个电路之一的接入。仲裁装置包括分拣机和仲裁员。分类器接收包括多个图像层的图像信号的位置信息，并且根据位置信息确定包括第一组和第二组的访问优先级。所述仲裁器接收所述接入优先级和所述多个请求中的至少一个请求，并且根据所述接入优先级和所述多个请求中的所述至少一个来授权对所述多个电路之一的接入。此外，多个电路中的每一个相应地产生每个图像层的数据。

27. 发明申请

US20110180775A1 PROGRAMMABLE METALLIZATION CELL WITH ION BUFFER LAYER 有权
标题翻译：具有离子缓冲层的可编程金属化电池
公开(公告)号：US20110180775A1
公开(公告)日：2011-07-28
申请号：US12692861
申请日：2010-01-25
申请人： Yuyu LIN , Feng-Ming Lee , Yi-Chou Chen
发明人： Yuyu LIN , Feng-Ming Lee , Yi-Chou Chen
IPC分类号： H01L45/00 , H01L29/18 , H01L21/06
CPC分类号： H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1266 , H01L45/145
摘要： A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.
摘要翻译：可编程金属化器件，包括第一电极; 存储层，其电耦合到所述第一电极并适于通过其导电桥的电解形成和破坏; 离子供给层，其含有能够扩散到所述存储层中的第一金属元素的离子源; 在离子供给层和存储层之间的导电离子缓冲层，并且允许所述离子的扩散; 以及电耦合到所述离子供应层的第二电极。电路耦合到器件以向第一和第二电极施加偏置电压，以引起包括存储器层中的第一金属元件的导电桥的产生和破坏。离子缓冲层可以通过降低第一金属元素被吸收到离子供给层中的可能性来改善导电桥的保留。

28. 发明授权

US07696503B2 Multi-level memory cell having phase change element and asymmetrical thermal boundary 有权
标题翻译：具有相变元件和不对称热边界的多层存储单元
公开(公告)号：US07696503B2
公开(公告)日：2010-04-13
申请号：US11837636
申请日：2007-08-13
申请人： Hsiang-Lan Lung , Yi-Chou Chen
发明人： Hsiang-Lan Lung , Yi-Chou Chen
IPC分类号： H01L29/02
CPC分类号： H01L45/143 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683 , Y10T29/49117
摘要： A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn away from the memory material asymmetrically along a line orthogonal to electric field lines between the electrodes.
摘要翻译：多级相变存储器单元具有第一和第二热隔离材料，该材料具有不同的导热性质，其位于与相变材料的第一和第二边界的导热关系中。因此，当施加电流以提高存储材料的温度时，沿着与电极之间的电场线正交的线不对称地将热量从存储材料拉出。

29. 发明授权

US07688619B2 Phase change memory cell and manufacturing method 有权
标题翻译：相变存储单元及其制造方法
公开(公告)号：US07688619B2
公开(公告)日：2010-03-30
申请号：US11612093
申请日：2006-12-18
申请人： Hsiang-Lan Lung , Rich Liu , Shih-Hung Chen , Yi-Chou Chen
发明人： Hsiang-Lan Lung , Rich Liu , Shih-Hung Chen , Yi-Chou Chen
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2213/53 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/165 , H01L45/1675
摘要： A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion.
摘要翻译：相变存储单元包括由相变元件电耦合的第一和第二电极。相变元件的至少一部分包括较高的复位转变温度部分和较低的复位转变温度部分。下复位转变温度部分包括可以通过电流通过从相对于较高复位转变温度部分的较低温度的大致结晶到大致非晶状态的相变区域。相变元件可以包括围绕内部，下部复位转变温度部分的外部，大体上管状的较高复位转变温度部分。

30. 发明授权

US07608503B2 Side wall active pin memory and manufacturing method 有权
标题翻译：侧壁有源针存储器及制造方法
公开(公告)号：US07608503B2
公开(公告)日：2009-10-27
申请号：US11285473
申请日：2005-11-21
申请人： Hsiang Lan Lung , Shih-Hung Chen , Yi-Chou Chen
发明人： Hsiang Lan Lung , Shih-Hung Chen , Yi-Chou Chen
IPC分类号： H01L21/8242
CPC分类号： H01L27/112 , G11C2213/52 , H01L21/0337 , H01L21/0338 , H01L27/115 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/124 , H01L45/144 , H01L45/1691
摘要： A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is about 40 nanometers or less.
摘要翻译：一种形成存储单元的方法包括：在叠层上形成包括第一电极，绝缘层上的绝缘层和绝缘层上的第二电极的堆叠。形成包括与第一和第二电极电连通的可编程电阻材料的侧壁间隔物。通过在堆叠的侧壁上沉积可编程电阻材料层来形成侧壁间隔物，各向异性地蚀刻可编程电阻材料层，以便在远离侧壁的区域中去除它，并根据所述方法选择性地蚀刻可编程电阻材料用于限定侧壁间隔物的宽度的图案。在本文所述的实施例中，宽度为约40纳米或更小。

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