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1. 发明授权

US06828081B2 Method and system for lithography using phase-change material 有权
公开(公告)号：US06828081B2
公开(公告)日：2004-12-07
申请号：US10315003
申请日：2002-12-10
申请人： Yi-Chou Chen , Chih-Yuan Lu , Hsiang-Lan Lung , Li-Hsin Chuang
发明人： Yi-Chou Chen , Chih-Yuan Lu , Hsiang-Lan Lung , Li-Hsin Chuang
IPC分类号： H01L2182
CPC分类号： H01L45/1213 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Methods and systems are provided for forming an electrical interconnect layer between two layers of an integrated circuit. The interconnect layer is formed using a material having a first electrical conductivity corresponding to a first state and a second electrical conductivity corresponding to a second state, where the first electrical conductivity is different from the second electrical conductivity. An area of the material of the interconnect layer may be selected, for example, using a mask. Then energy may be applied to the selected area to change the electrical conductivity of the material in the selected area of the interconnect layer. Thus, the present invention may be used to implement optical memory devices which may be read by an electrical circuit.

2. 发明授权

US06850432B2 Laser programmable electrically readable phase-change memory method and device 有权
标题翻译：激光可编程电可读相变存储器的方法和装置
公开(公告)号：US06850432B2
公开(公告)日：2005-02-01
申请号：US10223975
申请日：2002-08-20
申请人： Chih-Yuan Lu , Yi-Chou Chen
发明人： Chih-Yuan Lu , Yi-Chou Chen
IPC分类号： G11C16/02 , G11C16/10 , G11C16/18 , G11C11/00
CPC分类号： G11C13/0004 , G11C13/04 , G11C16/18 , G11C2213/72
摘要： Roughly described, a phase-change memory such as a chalcogenide-based memory is programmed optically and read electrically. No complex electrical circuits are required for programming the cells. On the other hand, this memory can be read by electrical circuitry directly. The read out speed is much faster than for optical disks, and integrated circuit chips made this way are more compatible with other electrical circuits than are optical disks. Thus memories according to the invention can have simple, low power-consuming, electrical circuits, and do not require slow and power-hungry disk drives for reading. The invention therefore provides a unique low power, fast read/write memory with simple electrical circuits.
摘要翻译：粗略地描述，诸如基于硫族化物的存储器之类的相变存储器被光学地编程并且被电读取。编程电池不需要复杂的电路。另一方面，该存储器可以直接由电路读取。读出速度比光盘快得多，而采用这种方式制成的集成电路芯片与其他电路比光盘更为兼容。因此，根据本发明的存储器可以具有简单的，低功耗的电路，并且不需要用于读取的缓慢且耗电的磁盘驱动器。因此，本发明提供了具有简单电路的独特的低功率，快速读/写存储器。

3. 发明授权

US07180767B2 Multi-level memory device and methods for programming and reading the same 有权
标题翻译：多级存储器件及其编程和读取方法
公开(公告)号：US07180767B2
公开(公告)日：2007-02-20
申请号：US10465012
申请日：2003-06-18
申请人： Yi Chou Chen , Chih-Yuan Lu
发明人： Yi Chou Chen , Chih-Yuan Lu
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069
摘要： A multilevel memory core includes a word line and a bit line. The multilevel memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to define multiple levels for storage where each of the multiple levels for storage is associated with a corresponding threshold voltage. Methods for reading the multilevel memory core also are described.
摘要翻译：多级存储器核心包括字线和位线。多级存储器核心还包括与字线和位线电通信的核心单元。核心单元包括阈值变化材料。阈值改变材料被编程为定义用于存储的多个级别，其中用于存储的多个级别中的每一个与相应的阈值电压相关联。还描述了读取多级存储器核心的方法。

4. 发明授权

US07236394B2 Transistor-free random access memory 有权
标题翻译：无晶体管随机存取存储器
公开(公告)号：US07236394B2
公开(公告)日：2007-06-26
申请号：US10464938
申请日：2003-06-18
申请人： Yi Chou Chen , Wen-Jer Tsai , Chih-Yuan Lu
发明人： Yi Chou Chen , Wen-Jer Tsai , Chih-Yuan Lu
IPC分类号： G11C11/34
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2213/77
摘要： A memory core includes a bit line and a word line. The memory core also includes a core cell in electrical communication with the word line and the bit line. The core cell includes a threshold changing material. The threshold changing material is programmed to enable access to the core cell based upon a voltage applied to the word line. Methods for accessing a memory core cell also are described.
摘要翻译：存储器核心包括位线和字线。存储器核心还包括与字线和位线电通信的核心单元。核心单元包括阈值变化材料。阈值改变材料被编程为使得能够基于施加到字线的电压来访问核心单元。还描述了访问存储器核心单元的方法。

5. 发明授权

US5943581A Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits 失效
标题翻译：制造用于高密度动态随机存取存储器（DRAM）电路的埋藏式电容器结构的方法
公开(公告)号：US5943581A
公开(公告)日：1999-08-24
申请号：US964808
申请日：1997-11-05
申请人： Chih-Yuan Lu , Janmye Sung
发明人： Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10858 , H01L27/10832
摘要： An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N.sup.+ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the device areas aligned over the N.sup.+ regions. Holes are etched in the epi layer to the N.sup.+ regions, and a selective wet etch removes the N.sup.+ doped regions to form cavities. A thin dielectric layer is deposited on the cavity walls, and an N.sup.+ polysilicon layer is deposited and polished back to form the buried reservoir capacitors. The N.sup.+ polysilicon in the holes forms the capacitor node contacts for the FETs in the device areas. The array of DRAM cells is completed by growing a gate oxide, depositing and patterning a first polycide layer to form FET gate electrodes on the device areas over the capacitors, thereby providing increased capacitance while reducing the cell area. Lightly doped source/drain (LDD) areas, sidewall spacers and heavily doped source/drain contacts are formed for the FETs. A node strap is formed between one source/drain contact and the node contact to make good electrical contact. An insulating layer is deposited having bit line contact holes, and a second polycide layer is patterned to form the bit lines for the DRAM.
摘要翻译：实现了使用新颖的埋藏式电容器的改进的DRAM单元。该方法在衬底中形成N +掺杂区域的阵列。在衬底上的外延层中形成P阱。围绕在N +区域上排列的器件区域周围形成场氧化物（FOX）。将孔在外延层中蚀刻到N +区，并且选择性湿蚀刻去除N +掺杂区以形成空穴。在空腔壁上沉积薄的电介质层，并且沉积并抛光N +多晶硅层以形成埋藏的储存电容器。孔中的N +多晶硅形成器件区域中的FET的电容器节点接触。通过生长栅极氧化物，沉积和图案化第一多晶硅层以在电容器上的器件区域上形成FET栅电极来完成DRAM单元的阵列，从而在减小电池面积的同时提供增加的电容。形成用于FET的轻掺杂源极/漏极（LDD）区域，侧壁间隔物和重掺杂源极/漏极接触。节点带形成在一个源极/漏极接触点和节点接触点之间以形成良好的电接触。沉积具有位线接触孔的绝缘层，并且图案化第二多晶硅化物层以形成用于DRAM的位线。

6. 发明授权

US5804480A method for forming a DRAM capacitor using HSG-Si technique and oxygen implant 失效
标题翻译：使用HSG-Si技术形成DRAM电容器的方法和氧注入
公开(公告)号：US5804480A
公开(公告)日：1998-09-08
申请号：US807441
申请日：1997-02-28
申请人： Chih-Yuan Lu , Horng-Huei Tseng
发明人： Chih-Yuan Lu , Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/205 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L27/10817 , H01L28/92
摘要： A method for forming a DRAM capacitor using a HSG-Si includes forming a dielectric layer over a substrate. A polysilicon layer is formed over the dielectric layer, and a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process. The HSG-Si layer includes a large number of silicon grains spaced apart on the surface of the polysilicon layer with the area of the polysilicon layer's surface being left exposed. Next, oxygen is implanted into the polysilicon layer using the silicon grains as an implant mask, thereby forming oxygen regions in the polysilicon layer. The HSG-Si layer is removed and the oxygen regions are annealed to transform the atom regions into oxide regions. Afterwards, the polysilicon layer is etched using the oxide regions as an etching mask, thereby forming a large number of trenches in the polysilicon layer. The oxide regions and portions of the polysilicon layer are removed to form a storage node, which serves as a bottom electrode of the DRAM cell capacitor.
摘要翻译：使用HSG-Si形成DRAM电容器的方法包括在衬底上形成电介质层。在电介质层上形成多晶硅层，使用初始相HSG-Si工艺在多晶硅层上形成半球状硅（HSG-Si）层。 HSG-Si层包括在多晶硅层的表面上间隔开的多个硅颗粒，多晶硅层的表面的面积被暴露。接下来，使用硅晶粒作为注入掩模将氧注入多晶硅层，从而在多晶硅层中形成氧区。除去HSG-Si层，对氧区进行退火，将原子区域变换为氧化物区域。之后，使用氧化物区域蚀刻多晶硅层作为蚀刻掩模，从而在多晶硅层中形成大量的沟槽。去除氧化物区域和多晶硅层的部分以形成用作DRAM单元电容器的底部电极的存储节点。

7. 发明授权

US5792680A Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor 失效
标题翻译：用自对准双槽CMOS器件和柱状电容器形成低成本DRAM单元的方法
公开(公告)号：US5792680A
公开(公告)日：1998-08-11
申请号：US756129
申请日：1996-11-25
申请人： Janmye Sung , Chih-Yuan Lu , Howard Clayton Kirsch
发明人： Janmye Sung , Chih-Yuan Lu , Howard Clayton Kirsch
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/108 , H01L21/8238
CPC分类号： H01L27/10852 , H01L27/1052 , H01L27/10817
摘要： The invention is a method of forming a reduced cost DRAM. The process has two embodiments for forming twin wells and two embodiments for forming pillar shaped capacitor electrodes. The twin well embodiments are simple low cost processes. The embodiments for forming the electrode pillars begin by forming a tungsten silicide conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. This first embodiment for fabricating the multiple pillar capacitor forms pillars of a smaller dimension than the resolution of the photolithography tool. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.
摘要翻译：本发明是一种形成降低成本的DRAM的方法。该方法具有用于形成双阱的两个实施例和用于形成柱状电容器电极的两个实施例。双阱实施例是简单的低成本处理。用于形成电极柱的实施例开始于在第一平坦化层上形成硅化钨导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于制造多支柱电容器的第一实施例形成比光刻工具的分辨率小的尺寸的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。

8. 发明授权

US5679596A Spot deposited polysilicon for the fabrication of high capacitance, DRAM devices 失效
标题翻译：点沉积多晶硅用于制造高电容DRAM设备
公开(公告)号：US5679596A
公开(公告)日：1997-10-21
申请号：US734061
申请日：1996-10-18
申请人： Chih-Yuan Lu
发明人： Chih-Yuan Lu
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method of increasing the surface area of a STC structure, used for high density, DRAM devices, has been developed. The process consists of creating multiple, narrow crevices in a polysilicon, bottom electrode structure. This is accomplished by initially depositing a discontinuous layer of spot polysilicon on a thin silicon oxide layer, with the thin silicon oxide layer overlying the polysilicon bottom electrode. The spot polysilicon feature is transferred to the underlying thin silicon oxide layer, via conventional etching procedures, creating multiple, narrow, structures of spot polysilicon overlying the thin silicon oxide. These structures are then used as a micro-mask to create multiple, narrow crevices, via etching of the underlying polysilicon bottom electrode. Removal of the micro-mask, formation of a thin dielectric layer, and creation of a polysilicon upper electrode, complete the STC fabrication sequence.
摘要翻译：已经开发了增加用于高密度DRAM器件的STC结构的表面积的方法。该过程包括在多晶硅，底部电极结构中产生多个狭窄的缝隙。这是通过最初在薄氧化硅层上沉积不连续的点多晶硅层来实现的，其中薄的氧化硅层覆盖多晶硅底部电极。通过常规蚀刻方法将点多晶硅特征转移到下面的薄氧化硅层，产生覆盖在薄氧化硅上的多点，窄的点状多晶硅结构。然后，通过蚀刻下面的多晶硅底部电极，将这些结构用作微型掩模以产生多个狭窄的缝隙。去除微掩模，形成薄介电层，以及产生多晶硅上电极，完成STC制造顺序。

9. 发明授权

US5652165A Method of forming a stacked capacitor with a double wall crown shape 失效
标题翻译：形成具有双壁冠形状的叠层电容器的方法
公开(公告)号：US5652165A
公开(公告)日：1997-07-29
申请号：US661251
申请日：1996-06-10
申请人： Chih-Yuan Lu , Horng-Huei Tseng
发明人： Chih-Yuan Lu , Horng-Huei Tseng
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： The present invention provides a method of manufacturing a stacked capacitor having a double walled crown shape. The method begins by providing a field effect transistor adjacent to a field oxide region in a substrate. Next, a first insulating layer and a barrier layer is formed over the resultant surface. A node contact opening is then etched in the barrier layer and the first insulation layer exposing a source region of the transistor. A first conductive layer is formed in the node contact opening and covers the first silicon nitride layer. A masking block is then formed over at least the node contact hole. First conductive spacers are then formed on the sidewalls of the masking block. Nitride spacers are formed on the sidewalls of the first conductive spacers. Second conductive spacers are formed on the sidewalls of the nitride spacers. The first conductive layer is anisotropically etched using the cylinder block, first conductive spacers, and the dielectric spacers as a mask. The masking block and the nitride spacers are removed thereby forming a double wall crown shape bottom electrode. A capacitor dielectric layer and top plate are formed to complete the capacitor.
摘要翻译：本发明提供一种制造具有双层冠状的叠层电容器的方法。该方法开始于提供与衬底中的场氧化物区域相邻的场效应晶体管。接下来，在所得表面上形成第一绝缘层和阻挡层。然后在阻挡层中蚀刻节点接触开口，并且第一绝缘层暴露晶体管的源极区域。第一导电层形成在节点接触开口中并覆盖第一氮化硅层。然后在至少节点接触孔上形成屏蔽块。然后在掩模块的侧壁上形成第一导电间隔物。氮化物间隔物形成在第一导电间隔物的侧壁上。第二导电间隔物形成在氮化物间隔物的侧壁上。使用气缸体，第一导电间隔件和电介质间隔件作为掩模对第一导电层进行各向异性蚀刻。去除掩模块和氮化物间隔物，从而形成双壁冠形底部电极。形成电容器电介质层和顶板以完成电容器。

10. 发明授权

US5395784A Method of manufacturing low leakage and long retention time DRAM 失效
标题翻译：制造低泄漏和长保留时间DRAM的方法
公开(公告)号：US5395784A
公开(公告)日：1995-03-07
申请号：US46777
申请日：1993-04-14
申请人： Chih-Yuan Lu , Nicky C. Lu , Hsiao-Chin Tuan
发明人： Chih-Yuan Lu , Nicky C. Lu , Hsiao-Chin Tuan
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10861 , H01L27/10808
摘要： A method for making a DRAM MOSFET integrated circuit and resulting device having low leakage and long retention time in a semiconductor wafer is described. A pattern of gate dielectric and gate electrode structures is provided over the semiconductor wafer having a first conductivity imparting dopant in the cell array region and the peripheral circuits region of the integrated circuit. The pattern of gate dielectric and gate electrode structures as a mask for ion implantation to form lightly doped regions of a second and opposite conductivity imparting dopant in the semiconductor wafer wherein certain of the lightly doped regions within the cell array region are to be bit line regions and capacitor node regions. A capacitor is formed within the cell array region. An interlevel dielectric insulating layer is formed over the surface of the structure. A highly doped bit line contact is formed to the bit line regions. The structure is heated to anneal out the ion implantation damage in the lightly doped regions caused by the ion implantation into the lightly doped regions and to cause outdiffusion from the doped bit line contact layer to form a highly doped bit line contact within certain of the lightly doped regions wherein the low leakage and long retention time are the resulting circuit characteristics.
摘要翻译：描述了制造DRAM MOSFET集成电路的方法以及在半导体晶片中具有低泄漏和长保留时间的所得器件。栅电介质和栅极电极结构的图案设置在半导体晶片上，该半导体晶片在单元阵列区域和集成电路的外围电路区域中具有赋予第一导电性的掺杂剂。作为用于离子注入的掩模的栅极电介质和栅电极结构的图案，以在半导体晶片中形成第二相反导电赋予掺杂剂的轻掺杂区域，其中单元阵列区域内的某些轻掺杂区域将是位线区域和电容器节点区域。在电池阵列区域内形成电容器。在结构的表面上形成层间绝缘层。高位掺杂的位线接触形成在位线区域。该结构被加热以退出在由轻离子注入到轻掺杂区域中引起的轻掺杂区域中的离子注入损伤，并引起来自掺杂位线接触层的扩散扩散，从而在轻微掺杂区域内形成高度掺杂的位线接触掺杂区域，其中低泄漏和长保留时间是得到的电路特性。

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