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21. 发明申请

US20120217579A1 High voltage device and manufacturing method thereof 审中-公开
标题翻译：高压器件及其制造方法
公开(公告)号：US20120217579A1
公开(公告)日：2012-08-30
申请号：US13136703
申请日：2011-08-08
申请人： Tsung-Yi Huang , Ying-Shiou Lin
发明人： Tsung-Yi Huang , Ying-Shiou Lin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0634 , H01L29/0692 , H01L29/1045 , H01L29/42368 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having a P (or N) type well and an isolation structure for defining a device region; a drift region, located in the device region, having a first region and a second region wherein the first region is an N (or P) type region, and the second region is a P (or N) type region or an N (or P) type region with different dopant concentration from the first region, and from top view, the first region and the second region include sub-regions distributed in the drift region; an N (or P) type source and drain; and a gate on a surface of the substrate, between the source and drain in the device region.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压装置包括：具有P（或N）型阱的衬底和用于限定器件区域的隔离结构; 位于器件区域中的漂移区域具有第一区域和第二区域，其中第一区域是N（或P）型区域，第二区域是P（或N）型区域或N（或 P）型区域，并且从顶视图看，第一区域和第二区域包括分布在漂移区域中的子区域; N（或P）型源极和漏极; 以及衬底的表面上的栅极，位于器件区域中的源极和漏极之间。

22. 发明申请

US20120187483A1 Double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20120187483A1
公开(公告)日：2012-07-26
申请号：US13066622
申请日：2011-04-20
申请人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
发明人： Ching-Yao Yang , Tsung-Yi Huang , Huan-Ping Chu , Hung-Der Su
IPC分类号： H01L29/78 , H01L21/8232 , H01L21/336
CPC分类号： H01L29/4238 , H01L21/28114 , H01L21/823425 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

23. 发明申请

US20120161235A1 Electrostatic discharge protection device and manufacturing method thereof 审中-公开
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20120161235A1
公开(公告)日：2012-06-28
申请号：US13317323
申请日：2011-10-15
申请人： Tsung-Yi Huang , Jin-Lian Su
发明人： Tsung-Yi Huang , Jin-Lian Su
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41758 , H01L27/0277 , H01L29/6659 , H01L29/7835
摘要： The present invention discloses an electrostatic discharge protection device and a manufacturing method thereof. The electrostatic discharge protection device includes: a substrate, a gate, two N type lightly doped drains, an N type source, an N type drain, and two N type doped regions extending downward beneath and in contact with the source and drain respectively, such that when the source and drain are conducted with each other, at least part of the current flows through the two downwardly extending doped regions to increase the electrostatic discharge protection voltage of the electrostatic discharge protection device.
摘要翻译：本发明公开了一种静电放电保护装置及其制造方法。静电放电保护装置包括：基板，栅极，两个N型轻掺杂漏极，N型源极，N型漏极和分别向下延伸并与源极和漏极接触的两个N型掺杂区域，当源极和漏极彼此导通时，至少部分电流流过两个向下延伸的掺杂区域以增加静电放电保护器件的静电放电保护电压。

24. 发明授权

US08183626B2 High-voltage MOS devices having gates extending into recesses of substrates 有权
标题翻译：具有延伸到衬底凹槽中的栅极的高压MOS器件
公开(公告)号：US08183626B2
公开(公告)日：2012-05-22
申请号：US13027097
申请日：2011-02-14
申请人： Chen-Liang Chu , Chun-Ting Liao , Tsung-Yi Huang , Fei-Yuh Chen
发明人： Chen-Liang Chu , Chun-Ting Liao , Tsung-Yi Huang , Fei-Yuh Chen
IPC分类号： H01L27/06
CPC分类号： H01L29/7833 , H01L29/4236 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66621 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.
摘要翻译：集成电路结构包括半导体衬底中的高电压阱（HVW）区域; HVW区域中的第一双扩散（DD）区域; 和HVW区域中的第二DD区域。第一DD区域和第二DD区域通过HVW区域的中间部分彼此间隔开。凹部从半导体衬底的顶表面延伸到HVW区域和第二DD区域的中间部分。栅极电介质延伸到凹部中并覆盖凹部的底部。栅极电极在栅极电介质上方。第一源/漏区在第一DD区。第二个源极/漏极区域位于第二个DD区域。

25. 发明授权

US08143130B1 Method of manufacturing depletion MOS device 有权
标题翻译：制造耗尽型MOS器件的方法
公开(公告)号：US08143130B1
公开(公告)日：2012-03-27
申请号：US12910051
申请日：2010-10-22
申请人： Tsung-Yi Huang
发明人： Tsung-Yi Huang
IPC分类号： H01L21/8236
CPC分类号： H01L27/0883 , H01L21/823412 , H01L21/823418 , H01L21/823462
摘要： The present invention discloses a method of manufacturing a depletion metal oxide semiconductor (MOS) device. The method includes: providing a substrate; forming a first conductive type well and an isolation region in the substrate to define a device area; defining a drift region, a source, a drain, and a threshold voltage adjustment region, and implanting second conductive type impurities to form the drift region, the source, the drain, and the threshold voltage adjustment region, respectively; defining a breakdown protection region between the drain and the threshold voltage adjustment region, and implanting first conductive type impurities to form the breakdown protection region; and forming a gate in the device area; wherein a part of the breakdown protection region is below the gate, and the breakdown protection region covers an edge of the threshold voltage adjustment region.
摘要翻译：本发明公开了一种制造耗尽金属氧化物半导体（MOS）器件的方法。该方法包括：提供衬底; 在衬底中形成第一导电类型阱和隔离区以限定器件区域; 限定漂移区域，源极，漏极和阈值电压调整区域，以及分别植入第二导电类型杂质以形成漂移区域，源极，漏极和阈值电压调整区域; 限定漏极和阈值电压调整区域之间的击穿保护区域，以及注入第一导电型杂质以形成击穿保护区域; 以及在所述设备区域中形成栅极; 其中所述击穿保护区域的一部分在所述栅极下方，所述击穿保护区域覆盖所述阈值电压调整区域的边缘。

26. 发明授权

US07960786B2 Breakdown voltages of ultra-high voltage devices by forming tunnels 有权
标题翻译：通过形成隧道的超高压装置的击穿电压
公开(公告)号：US07960786B2
公开(公告)日：2011-06-14
申请号：US12170246
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 所述第一导电类型的场环占据所述HVW的顶部部分，其中所述预HVW，所述HVW和所述场环中的至少一个包括至少两个隧道; 在场环上的绝缘区域和HVW的一部分; 在HVW中的漏极区域并且邻近绝缘区域; 绝缘区域的一部分上的栅电极; 以及栅极电极的与漏极区域相反的一侧的源极区域。

27. 发明授权

US07768071B2 Stabilizing breakdown voltages by forming tunnels for ultra-high voltage devices 有权
标题翻译：通过形成超高压设备的隧道来稳定击穿电压
公开(公告)号：US07768071B2
公开(公告)日：2010-08-03
申请号：US12170285
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Puo-Yu Chiang
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Puo-Yu Chiang
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 第一导电类型的场环占据HVW的顶部; 以及预HVW和HVW中的第一导电类型的隧道，并且电场连接场环和半导体衬底。

28. 发明授权

US07723785B2 High performance power MOS structure 有权
标题翻译：高性能功率MOS结构
公开(公告)号：US07723785B2
公开(公告)日：2010-05-25
申请号：US11831689
申请日：2007-07-31
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.
摘要翻译：半导体器件包括设置在衬底中的源区和漏区，其中源区和漏区具有第一类掺杂剂; 形成在所述基板上的栅极电极，横向插入在所述源极和漏极区域之间; 栅极间隔物，设置在所述基板上，并且在所述源极区域和所述栅极电极之间的横向上与所述栅电极的一侧相邻; 以及嵌入栅极间隔物中的导电特征。

29. 发明申请

US20090032868A1 HIGH PERFORMANCE POWER MOS STRUCTURE 有权
标题翻译：高性能功率MOS结构
公开(公告)号：US20090032868A1
公开(公告)日：2009-02-05
申请号：US11831689
申请日：2007-07-31
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.
摘要翻译：半导体器件包括设置在衬底中的源区和漏区，其中源区和漏区具有第一类掺杂剂; 形成在所述基板上的栅极电极，横向插入在所述源极和漏极区域之间; 栅极间隔物，设置在所述基板上，并且在所述源极区域和所述栅极电极之间的横向上与所述栅电极的一侧相邻; 以及嵌入栅极间隔物中的导电特征。

30. 发明申请

US20080211026A1 Coupling well structure for improving HVMOS performance 审中-公开
标题翻译：耦合井结构，以改善HVMOS性能
公开(公告)号：US20080211026A1
公开(公告)日：2008-09-04
申请号：US11594508
申请日：2006-11-08
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L23/62
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

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