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21. 发明申请

US20140038428A1 Self-Assembled Monolayer for Pattern Formation 有权
标题翻译：自组装单层模式形成
公开(公告)号：US20140038428A1
公开(公告)日：2014-02-06
申请号：US13567250
申请日：2012-08-06
申请人： Tsung-Min Huang , Chung-Ju Lee , Chien-Hua Huang
发明人： Tsung-Min Huang , Chung-Ju Lee , Chien-Hua Huang
IPC分类号： H01L21/027
CPC分类号： H01L21/0338 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L21/76816
摘要： The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.
摘要翻译：本公开涉及制造半导体器件的方法。在一些实施例中，半导体器件包括图案化表面。该图案可以由自组装单层形成。所公开的方法提供可以快速沉积的自组装单层，从而增加生产量和降低成本，以及提供具有基本均匀形状的图案。

22. 发明申请

US20070063290A1 METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：金属氧化物半导体晶体管
公开(公告)号：US20070063290A1
公开(公告)日：2007-03-22
申请号：US11162693
申请日：2005-09-20
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/6653 , H01L21/28518 , H01L21/31111 , H01L29/6659
摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.
摘要翻译：提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。首先，在基板上形成栅极结构。然后，在栅极结构的相应侧壁上形成偏移间隔物。执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。在偏置间隔物的相应侧壁上形成其它间隔物。此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。然后，在源极和漏极的表面上形成金属硅化物层。在金属硅化物层的表面上形成氧化物层。去除间隔物，并在衬底上形成蚀刻停止层。通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

23. 发明授权

US07105454B2 Use of ammonia for etching organic low-k dielectrics 有权
公开(公告)号：US07105454B2
公开(公告)日：2006-09-12
申请号：US10762969
申请日：2004-01-21
申请人： Chok W. Ho , Kuo-Lung Tang , Chung-Ju Lee
发明人： Chok W. Ho , Kuo-Lung Tang , Chung-Ju Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/31138 , H01L21/31144
摘要： Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.

24. 发明授权

US06893969B2 Use of ammonia for etching organic low-k dielectrics 失效
标题翻译：使用氨蚀刻有机低k电介质
公开(公告)号：US06893969B2
公开(公告)日：2005-05-17
申请号：US09782446
申请日：2001-02-12
申请人： Chok W. Ho , Kuo-Lung Tang , Chung-Ju Lee
发明人： Chok W. Ho , Kuo-Lung Tang , Chung-Ju Lee
IPC分类号： B44C1/22 , C03C15/00 , C23F1/00 , H01L21/302 , H01L21/306 , H01L21/311 , H01L21/768 , H01K21/302
CPC分类号： H01L21/31138 , H01L21/31144
摘要： Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.
摘要翻译：使用氨，NH 3作为活性蚀刻剂蚀刻有机低k电介质的方法。使用氨的工艺导致有机低k电介质材料的蚀刻速率至少比使用N 2 / H 2化学物质在相似工艺条件下的蚀刻速率的两倍。不同之处在于，在工艺化学中，NH 3与N 2的电离电位低得多，这在相似的工艺条件下导致显着更高的等离子体密度和蚀刻剂浓度。

25. 发明授权

US6159822A Self-planarized shallow trench isolation 有权
标题翻译：自平坦化浅沟槽隔离
公开(公告)号：US6159822A
公开(公告)日：2000-12-12
申请号：US324136
申请日：1999-06-02
申请人： Fu-Liang Yang , Chung-Ju Lee , Meow-Ru Sheu
发明人： Fu-Liang Yang , Chung-Ju Lee , Meow-Ru Sheu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A method for implementing self-planarized shallow trench isolation in an integrated circuit. A planarized insulator oxide layer is formed after shallow trench isolation is etched and insulator oxide layer is deposited and etched back. The corners of silicon nitride layer over active area are exposed after the etch back step. Then, a silicon nitride cap layer is deposited. A non-critical photoresist patterning is used to expose the bigger active regions. Afterward, the cap layer on the bigger active regions is removed. Then, the insulator oxide layer under the cap layer is removed by wet etch after stripping of photoresist. Subsequently, wet etch is used to remove the cap layer and the silicon nitride layer. Finally, the self-planarized shallow trench isolation processes are completed after the pad oxide is removed.
摘要翻译：一种在集成电路中实现自平坦化浅沟槽隔离的方法。在蚀刻浅沟槽隔离并沉积并回蚀刻绝缘体氧化物层之后形成平坦化的绝缘体氧化物层。在有效区域之后的氮化硅层的角部在回蚀步骤之后被暴露。然后，沉积氮化硅盖层。使用非关键的光致抗蚀剂图案化来暴露较大的活性区域。之后，去除较大活性区域上的盖层。然后，在剥离光致抗蚀剂之后，通过湿蚀刻去除覆盖层下的绝缘体氧化物层。随后，使用湿蚀刻去除覆盖层和氮化硅层。最后，在去除衬垫氧化物之后完成自平坦化的浅沟槽隔离工艺。

26. 发明申请

US20140021612A1 SEMICONDUCTOR DEVICE AND FABRICATING PROCESS FOR THE SAME 有权
标题翻译：半导体器件及其制造工艺
公开(公告)号：US20140021612A1
公开(公告)日：2014-01-23
申请号：US13553535
申请日：2012-07-19
申请人： Chien-Hua HUANG , Chung-Ju Lee , Tsung-Min Huang
发明人： Chien-Hua HUANG , Chung-Ju Lee , Tsung-Min Huang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/02123 , H01L21/31105 , H01L21/76804 , H01L21/76813 , H01L21/76831 , H01L21/76832 , H01L21/76867 , H01L21/76897 , H01L21/76898 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.
摘要翻译：提供了一种半导体器件及其制造方法。半导体器件包括具有一部分反应性材料的基底层; 以及自组装分子与在该部分上形成的反应性材料反应的自组装保护层。

27. 发明授权

US08507996B2 Block contact plugs for MOS devices 有权
标题翻译：块接触器用于MOS器件
公开(公告)号：US08507996B2
公开(公告)日：2013-08-13
申请号：US12789046
申请日：2010-05-27
申请人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
发明人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
IPC分类号： H01L23/528
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
摘要翻译：集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。第二接触插塞的横截面积小于第一接触插塞的横截面面积。

28. 发明授权

US07595234B2 Fabricating method for a metal oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US07595234B2
公开(公告)日：2009-09-29
申请号：US11532100
申请日：2006-09-15
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28518 , H01L21/31111 , H01L29/6659
摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.
摘要翻译：提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。首先，在基板上形成栅极结构。然后，在栅极结构的相应侧壁上形成偏移间隔物。执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。在偏置间隔物的相应侧壁上形成其它间隔物。此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。然后，在源极和漏极的表面上形成金属硅化物层。在金属硅化物层的表面上形成氧化物层。去除间隔物，并在衬底上形成蚀刻停止层。通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

29. 发明申请

US20070066041A1 FABRICATING METHOD FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：一种金属氧化物半导体晶体管的制造方法
公开(公告)号：US20070066041A1
公开(公告)日：2007-03-22
申请号：US11532100
申请日：2006-09-15
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
IPC分类号： H01L21/4763
CPC分类号： H01L29/6653 , H01L21/28518 , H01L21/31111 , H01L29/6659
摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.
摘要翻译：提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。首先，在基板上形成栅极结构。然后，在栅极结构的相应侧壁上形成偏移间隔物。执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。在偏置间隔物的相应侧壁上形成其它间隔物。此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。然后，在源极和漏极的表面上形成金属硅化物层。在金属硅化物层的表面上形成氧化物层。去除间隔物，并在衬底上形成蚀刻停止层。通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

30. 发明申请

US20050003676A1 Use of ammonia for etching organic low-k dielectrics 有权
公开(公告)号：US20050003676A1
公开(公告)日：2005-01-06
申请号：US10762969
申请日：2004-01-21
申请人： Chok Ho , Kuo-Lung Tang , Chung-Ju Lee
发明人： Chok Ho , Kuo-Lung Tang , Chung-Ju Lee
IPC分类号： B44C1/22 , C03C15/00 , C23F1/00 , H01L21/302 , H01L21/306 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31138 , H01L21/31144
摘要： Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.

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