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1. 发明授权

US07595234B2 Fabricating method for a metal oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US07595234B2
公开(公告)日：2009-09-29
申请号：US11532100
申请日：2006-09-15
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28518 , H01L21/31111 , H01L29/6659
摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.
摘要翻译：提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。首先，在基板上形成栅极结构。然后，在栅极结构的相应侧壁上形成偏移间隔物。执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。在偏置间隔物的相应侧壁上形成其它间隔物。此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。然后，在源极和漏极的表面上形成金属硅化物层。在金属硅化物层的表面上形成氧化物层。去除间隔物，并在衬底上形成蚀刻停止层。通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

2. 发明申请

US20070066041A1 FABRICATING METHOD FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：一种金属氧化物半导体晶体管的制造方法
公开(公告)号：US20070066041A1
公开(公告)日：2007-03-22
申请号：US11532100
申请日：2006-09-15
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
IPC分类号： H01L21/4763
CPC分类号： H01L29/6653 , H01L21/28518 , H01L21/31111 , H01L29/6659
摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.
摘要翻译：提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。首先，在基板上形成栅极结构。然后，在栅极结构的相应侧壁上形成偏移间隔物。执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。在偏置间隔物的相应侧壁上形成其它间隔物。此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。然后，在源极和漏极的表面上形成金属硅化物层。在金属硅化物层的表面上形成氧化物层。去除间隔物，并在衬底上形成蚀刻停止层。通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

3. 发明申请

US20070063290A1 METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
标题翻译：金属氧化物半导体晶体管
公开(公告)号：US20070063290A1
公开(公告)日：2007-03-22
申请号：US11162693
申请日：2005-09-20
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/6653 , H01L21/28518 , H01L21/31111 , H01L29/6659
摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.
摘要翻译：提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。首先，在基板上形成栅极结构。然后，在栅极结构的相应侧壁上形成偏移间隔物。执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。在偏置间隔物的相应侧壁上形成其它间隔物。此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。然后，在源极和漏极的表面上形成金属硅化物层。在金属硅化物层的表面上形成氧化物层。去除间隔物，并在衬底上形成蚀刻停止层。通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

4. 发明授权

US07214988B2 Metal oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管
公开(公告)号：US07214988B2
公开(公告)日：2007-05-08
申请号：US11162693
申请日：2005-09-20
申请人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
发明人： Po-Chao Tsao , Chang-Chi Huang , Ming-Tsung Chen , Yi-Yiing Chiang , Yu-Lan Chang , Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
IPC分类号： H01L29/76
CPC分类号： H01L29/6653 , H01L21/28518 , H01L21/31111 , H01L29/6659
摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.
摘要翻译：提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。首先，在基板上形成栅极结构。然后，在栅极结构的相应侧壁上形成偏移间隔物。执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。在偏置间隔物的相应侧壁上形成其它间隔物。此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。然后，在源极和漏极的表面上形成金属硅化物层。在金属硅化物层的表面上形成氧化物层。去除间隔物，并在衬底上形成蚀刻停止层。通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

5. 发明申请

US20060110688A1 Etching process compatible with DUV lithography 审中-公开
标题翻译：蚀刻工艺兼容DUV光刻
公开(公告)号：US20060110688A1
公开(公告)日：2006-05-25
申请号：US10993593
申请日：2004-11-19
申请人： Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
发明人： Chung-Ju Lee , Chih-Ning Wu , Kuan-Yang Liao
IPC分类号： G03F7/36
CPC分类号： G03F7/405 , G03F7/40
摘要： An etching process compatible with DUV lithography is described. A mask layer is previously formed over a material layer to be etched through a DUV lithography process of 193 nm or 157 nm. Then, plasma etching is performed to pattern the material layer using the mask layer as an etching mask, wherein the etching gas causes a protective layer to form on the surface of the mask layer. The etching gas of the plasma etching includes at least a halogen-containing gas and Xe, wherein the halogen can be F, Cl, Br or a combination thereof.
摘要翻译：描述了与DUV光刻相兼容的蚀刻工艺。预先通过193nm或157nm的DUV光刻工艺在待蚀刻的材料层上形成掩模层。然后，进行等离子体蚀刻，使用掩模层作为蚀刻掩模对材料层进行图案化，其中蚀刻气体在掩模层的表面上形成保护层。等离子体蚀刻的蚀刻气体至少包含含卤素的气体和Xe，其中卤素可以是F，Cl，Br或其组合。

6. 发明申请

US20070054447A1 Multistep etching method 审中-公开
标题翻译：多步蚀刻法
公开(公告)号：US20070054447A1
公开(公告)日：2007-03-08
申请号：US11221487
申请日：2005-09-07
申请人： Hsin Tai , Chung-Ju Lee , Chih-Ning Wu
发明人： Hsin Tai , Chung-Ju Lee , Chih-Ning Wu
IPC分类号： H01L21/8234 , H01L21/302 , H01L21/3205 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： A multi-step etching method is provided. First, a substrate including a gate over the substrate and a spacer over the gate is provided. Then, an anisotropic etching step is performed for etching a first region and a second region in the substrate at two sides of the gate. Thereafter, an isotropic etching step is performed for etching a first external region under the spacer and adjacent to the first region, and etching a second external region under the spacer and adjacent to the second region. Then, a filling step is performed for filling a material into the first region, the first external region, the second region and the second external region.
摘要翻译：提供了多步蚀刻方法。首先，提供包括在衬底上的栅极和栅极上的间隔物的衬底。然后，进行各向异性蚀刻步骤，以蚀刻栅极两侧的基板中的第一区域和第二区域。此后，进行各向同性蚀刻步骤，用于蚀刻间隔物下方的第一外部区域并与第一区域相邻，并且蚀刻间隔物下方的第二外部区域并与第二区域相邻。然后，进行用于将材料填充到第一区域，第一外部区域，第二区域和第二外部区域中的填充步骤。

7. 发明授权

US07338910B2 Method of fabricating semiconductor devices and method of removing a spacer 有权
标题翻译：制造半导体器件的方法和去除间隔物的方法
公开(公告)号：US07338910B2
公开(公告)日：2008-03-04
申请号：US11162952
申请日：2005-09-29
申请人： Chung-Ju Lee , Chih-Ning Wu , Wei-Tsun Shiau
发明人： Chung-Ju Lee , Chih-Ning Wu , Wei-Tsun Shiau
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76834 , H01L21/28518 , H01L21/31111
摘要： A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on the top or the surface of the semiconductor substrate and the electrode; and removing the spacer by steps of performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant. With respect to another aspect, a method of removing a spacer is also disclosed. The method includes performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant.
摘要翻译：公开了制造半导体器件的方法。该方法包括在半导体衬底上限定电极; 在所述电极的至少一个侧壁上形成间隔物; 在所述半导体衬底上使用所述间隔件作为掩模进行处理操作，并在所述半导体衬底和所述电极的顶部或表面上形成材料层; 并且通过在100℃至150℃的温度范围内进行湿蚀刻工艺的步骤去除间隔物，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。关于另一方面，还公开了一种去除间隔物的方法。该方法包括在100℃至150℃范围内的温度下进行湿蚀刻工艺，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。

8. 发明授权

US07491615B2 Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors 有权
标题翻译：制造应变硅晶体管和应变硅CMOS晶体管的方法
公开(公告)号：US07491615B2
公开(公告)日：2009-02-17
申请号：US11162798
申请日：2005-09-23
申请人： Chih-Ning Wu , Hsin Tai , Chung-Ju Lee , Wei-Tsun Shiau
发明人： Chih-Ning Wu , Hsin Tai , Chung-Ju Lee , Wei-Tsun Shiau
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.
摘要翻译：制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底在其上包含栅极结构; 执行蚀刻工艺以形成对应于半导体衬底内的栅极结构的两个凹部; 在半导体衬底上进行氧冲洗; 对所述半导体衬底进行清洁处理; 并且在每个用于形成源/漏区的凹槽中执行选择性外延生长（SEG）以形成外延层。

9. 发明授权

US08835304B2 Method of semiconductor integrated circuit fabrication 有权
标题翻译：半导体集成电路制造方法
公开(公告)号：US08835304B2
公开(公告)日：2014-09-16
申请号：US13599764
申请日：2012-08-30
申请人： Chih Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
发明人： Chih Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
IPC分类号： H01L21/00
CPC分类号： H01L21/76852 , H01L21/7682 , H01L21/76885 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature.
摘要翻译：公开了制造半导体集成电路（IC）的方法。该方法包括提供基板。牺牲层（SL）在衬底上形成并图案化。图案化SL具有多个开口。该方法还包括在开口中形成金属层，然后移除图案化的SL以横向暴露金属层的至少一部分以形成具有与开口基本相同的轮廓的金属特征。电介质层沉积在金属特征的侧面上。

10. 发明申请

US20130334700A1 ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT 有权
标题翻译： ETCH损伤和无菌双金属金属互连
公开(公告)号：US20130334700A1
公开(公告)日：2013-12-19
申请号：US13526640
申请日：2012-06-19
申请人： Sunil Kumar Singh , Chung-Ju Lee , Tien-I Bao
发明人： Sunil Kumar Singh , Chung-Ju Lee , Tien-I Bao
IPC分类号： H01L23/48 , H01L21/283 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76831 , H01L21/76835 , H01L21/76877 , H01L21/76879 , H01L21/76885 , H01L23/481 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1026 , H01L2221/1031 , H01L2221/1036 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.
摘要翻译：一种形成用于半导体器件的双镶嵌金属互连的方法。该方法包括形成低k电介质层，通过低k电介质层形成通孔，沉积牺牲层，通过牺牲层形成沟槽，用金属填充通孔和沟槽，去除牺牲层，然后沉积极低k电介质层填充沟槽之间。该方法允许形成用于第二级双镶嵌结构的极低k电介质层，同时通过沟槽蚀刻和沟槽金属沉积等工艺避免对该层的损伤。该方法具有避免通孔级电介质和沟槽级电介质之间的蚀刻停止层的额外优点。

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