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21. 发明授权

US06700827B2 Cam circuit with error correction 失效
标题翻译：具有误差校正的凸轮电路
公开(公告)号：US06700827B2
公开(公告)日：2004-03-02
申请号：US10226512
申请日：2002-08-23
申请人： Chuen-Der Lien , Michael J. Miller
发明人： Chuen-Der Lien , Michael J. Miller
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C11/4125 , G11C15/043 , G11C15/046
摘要： A CAM circuit including a RAM array, a CAM array, a control/interface circuit, and an error detection and correction (EDC) circuit. The control/interface circuit systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually refreshing data stored in the CAM array. The RAM array also stores check bits for each data word that can be generated by the EDC circuit when the data words are initially written to the CAM circuit. During the refresh operation, data words and associated check bits are read from the RAM array and transmitted to the EDC circuit. The EDC circuit analyzes each data word and associated check bits to detect errors, and corrects the data word, if necessary, before sending the data word to the CAM array.
摘要翻译：包括RAM阵列，CAM阵列，控制/接口电路和错误检测和校正（EDC）电路的CAM电路。控制/接口电路系统地将数据从RAM阵列写入CAM阵列，从而通过持续刷新存储在CAM阵列中的数据来防止软错误。当数据字最初写入CAM电路时，RAM阵列还存储可由EDC电路产生的每个数据字的校验位。在刷新操作期间，从RAM阵列读取数据字和相关的校验位，并发送到EDC电路。 EDC电路分析每个数据字和相关的检查位以检测错误，如果需要，在将数据字发送到CAM阵列之前校正数据字。

22. 发明授权

US06563754B1 DRAM circuit with separate refresh memory 有权
标题翻译： DRAM电路具有单独的刷新存储器
公开(公告)号：US06563754B1
公开(公告)日：2003-05-13
申请号：US09781524
申请日：2001-02-08
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C700
CPC分类号： G11C11/4125 , G11C15/04 , G11C15/043 , G11C15/046
摘要： A DRAM circuit including a first DRAM array used solely for refresh operations, and the second DRAM array for performing logic operations that is refreshed using data read from the first DRAM array. Specifically, data is read only from the first DRAM array during a read phase of the refresh operation, and is written to both the first DRAM array and the second DRAM array during the write phase of the refresh operation. Accordingly, the second DRAM array is able to simultaneously perform any type of logic operation without delay or disturbance caused by accessing the second DRAM array during the read phase. In one embodiment, the second DRAM array includes DRAM CAM cells that perform data matching operations using the data refreshed from the first DRAM array, which includes conventional DRAM memory cells. During read operations, because the data values stored in the first DRAM array and the second DRAM array are identical, data values are read from the conventional DRAM memory cells of the first DRAM array, instead of from the DRAM CAM cells.
摘要翻译：包括仅用于刷新操作的第一DRAM阵列的DRAM电路和用于执行使用从第一DRAM阵列读取的数据刷新的逻辑运算的第二DRAM阵列。具体地说，在刷新操作的读取阶段期间，数据仅从第一DRAM阵列读取，并且在刷新操作的写入阶段被写入第一DRAM阵列和第二DRAM阵列。因此，第二DRAM阵列能够在读取阶段期间同时执行任何类型的逻辑运算，而不会由于访问第二DRAM阵列而引起延迟或干扰。在一个实施例中，第二DRAM阵列包括使用从包括常规DRAM存储器单元的第一DRAM阵列刷新的数据执行数据匹配操作的DRAM CAM单元。在读取操作期间，由于存储在第一DRAM阵列和第二DRAM阵列中的数据值相同，所以从第一DRAM阵列的常规DRAM存储单元而不是从DRAM CAM单元读取数据值。

23. 发明授权

US06470418B1 Pipelining a content addressable memory cell array for low-power operation 有权
标题翻译：内置可寻址存储单元阵列，用于低功耗操作
公开(公告)号：US06470418B1
公开(公告)日：2002-10-22
申请号：US09232413
申请日：1999-01-15
申请人： Chuen-Der Lien , Chau-Chin Wu , John R. Mick
发明人： Chuen-Der Lien , Chau-Chin Wu , John R. Mick
IPC分类号： G06F1200
CPC分类号： G06F17/30982 , G11C7/1039 , G11C15/00
摘要： A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.
摘要翻译：一种内容寻址存储器（CAM）系统，其包括分别产生具有较高和较低优先级的第一和第二组匹配控制信号的第一和第二CAM阵列。第一个CAM阵列在第一个存储器周期中被使能，并且分析第一组匹配控制信号。如果在第一CAM阵列中存在匹配，则使能第一优先级编码器来处理第一组匹配控制信号。如果不存在匹配，则不启用第一优先级编码器，并且启动第二存储器周期。第二个CAM阵列在第二个存储周期中被使能，第二组信号被分析。如果在第二CAM阵列中存在匹配，则使能第二优先级编码器来处理第二组匹配控制信号。如果不存在匹配，则不启用第二优先级编码器。

24. 发明授权

US06373739B1 Quad CAM cell with minimum cell size 有权
标题翻译：具有最小单元尺寸的四边形CAM单元
公开(公告)号：US06373739B1
公开(公告)日：2002-04-16
申请号：US09731160
申请日：2000-12-06
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A four-state (quad) CAM cell that stores one of four logic values: a logic high value, a logic low value, a logic high don't care value, and a logic low don't care value. Each quad CAM cell includes a first memory cell, a second memory cell, a comparator circuit, and a control switch. The first memory cell stores a data value (i.e., logic high value or logic low value), and transmits this stored data value to the comparator circuit. The second memory cell stores a care/don't care data value that is transmitted to the control switch. Portions of the comparator circuit and the control switch form a discharge path between a match line and a discharge line connected to the quad CAM cell. The control switch is controlled by the care/don't care value to open/close a first part of the discharge path. The comparator circuit is controlled to open a second part of the discharge path when, for example, the stored data value is equal to an applied data value.
摘要翻译：存储四个逻辑值之一的四状态（四）CAM单元：逻辑高电平值，逻辑低电平值，逻辑高电平无关值，逻辑低电平无关。每个四边形CAM单元包括第一存储单元，第二存储单元，比较器电路和控制开关。第一存储单元存储数据值（即，逻辑高值或逻辑低值），并将该存储的数据值发送到比较器电路。第二存储器单元存储发送到控制开关的保养/不关心数据值。比较器电路和控制开关的部分在匹配线和连接到四边形CAM单元的放电线之间形成放电路径。控制开关由注意/不关心的值来控制，以打开/关闭排放路径的第一部分。当例如所存储的数据值等于所应用的数据值时，控制比较器电路以打开放电路径的第二部分。

25. 发明授权

US06266263B1 CAM array with minimum cell size 有权
标题翻译：具有最小单元格大小的CAM阵列
公开(公告)号：US06266263B1
公开(公告)日：2001-07-24
申请号：US09678502
申请日：2000-10-02
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A CAM cell array is disclosed in which a comparator function is performed by incorporating a selected transistor of each CAM cell latch into a signal path extending between a match line and a second (e.g., charge or discharge) line. A first terminal of the selected transistor is connected to the match line (or the second line), a second terminal is connected to an internal node of the latch, and a gate terminal of the selected transistor is controlled by the data value stored in the latch. The internal node of the latch is connected through a control transistor having a gate terminal connected to receive an applied data value. When the applied data value is equal to the stored data value, the match line is coupled to the second line along a signal path passing through the selected transistor and the pass transistor. During programming (i.e., when data values are written to the latch), the match line (or second line) carries a low/high voltage signal needed to set (flip) the latch into a desired state.
摘要翻译：公开了一种CAM单元阵列，其中通过将每个CAM单元锁存器的所选晶体管并入在匹配线和第二（例如充电或放电）线之间延伸的信号路径中来执行比较器功能。所选择的晶体管的第一端子连接到匹配线（或第二线），第二端子连接到锁存器的内部节点，并且所选晶体管的栅极端子由存储在所述晶体管中的数据值控制锁定。锁存器的内部节点通过连接有栅极端子的控制晶体管连接以接收施加的数据值。当应用的数据值等于存储的数据值时，匹配线沿着通过所选晶体管和传输晶体管的信号路径耦合到第二线。在编程期间（即，当数据值被写入锁存器时），匹配线（或第二线）承载将锁存器设置（翻转）到期望状态所需的低/高电压信号。

26. 发明授权

US6128207A Low-power content addressable memory cell 有权
标题翻译：低功耗内容可寻址存储单元
公开(公告)号：US6128207A
公开(公告)日：2000-10-03
申请号：US185057
申请日：1998-11-02
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a V.sub.CC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the V.sub.CC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the V.sub.CC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the V.sub.CC supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match sense line prior to a compare operation. If the data value stored in the CAM cell does not match the comparison data value, the match sense line is pulled down. The signal swing of the match sense line is smaller than the V.sub.CC supply voltage. For example, the signal swing on the match sense line can be as low as one transistor threshold voltage.
摘要翻译：一种内容可寻址存储器（CAM）单元，其包括响应于VCC电源电压工作的静态随机存取存储器（SRAM）单元。耦合到SRAM单元的第一组位线用于将数据值传送到SRAM单元和从SRAM单元传送数据值。在第一组位线上发送的信号具有等于VCC电源电压的信号摆幅。第二组位线被耦合以接收比较数据值。在第二组位线上发送的信号具有小于VCC电源电压的信号摆幅。例如，第二组位线上的信号摆幅可以低至两个晶体管阈值电压。第二组位线的电源电压低于VCC电源电压。提供了一种传感器电路，用于将存储在CAM单元中的数据值与比较数据值进行比较。传感器电路在比较操作之前对匹配检测线进行预充电。如果存储在CAM单元中的数据值与比较数据值不匹配，则下拉匹配检测线。匹配检测线的信号摆幅小于VCC电源电压。例如，匹配检测线上的信号摆幅可以低至一个晶体管阈值电压。

27. 发明授权

US6065973A Memory cell having active regions without N+ implants 失效
标题翻译：存储单元具有没有N +种植体的活动区域
公开(公告)号：US6065973A
公开(公告)日：2000-05-23
申请号：US802512
申请日：1997-02-20
申请人： Chuen-Der Lien , Pailu D. Wang
发明人： Chuen-Der Lien , Pailu D. Wang
IPC分类号： H01L27/11 , H01L29/08 , H01L29/78 , H01L21/8244
CPC分类号： H01L29/0847 , H01L27/1104 , H01L29/7833 , Y10S257/903 , Y10S257/904
摘要： Lightly doped active regions in a semiconductor structure reduce occurrences of pipeline defects. The light doped active region are typically employed where performance is not adversely affected. For example, in memory cells, pass transistors have lightly doped drains which directly connect to bit lines. A pass transistor of this type can have the source more heavily doped than the drain. Alternatively, drains and sources of pass transistors are lightly doped. Drains of pull-down transistors can also be lightly doped. The difference in doping of active regions does not increase fabrication processing steps because conventionally active regions are formed by two doping steps to create a lightly doped portions adjacent gates where field strength is highest. The invention changes such processes by covering the desired lightly active regions with the mask used during a second doping process.
摘要翻译：半导体结构中的轻掺杂有源区减少了管道缺陷的发生。通常在没有不利地影响性能的情况下使用光掺杂有源区。例如，在存储器单元中，传输晶体管具有直接连接到位线的轻掺杂漏极。这种类型的传输晶体管可以具有比漏极更重的掺杂源。或者，漏极和漏极源极轻掺杂。下拉式晶体管的漏极也可以轻掺杂。有源区域的掺杂差异不会增加制造处理步骤，因为常规有效区域通过两个掺杂步骤形成，以产生场强最高的邻近栅极的轻掺杂部分。本发明通过在第二掺杂过程中使用的掩模覆盖所需的轻度活性区域来改变这种方法。

28. 发明授权

US06031267A Compact static RAM cell 失效
标题翻译：紧凑的静态RAM单元
公开(公告)号：US06031267A
公开(公告)日：2000-02-29
申请号：US114580
申请日：1998-07-13
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H01L21/8238 , H01L21/8244 , H01L27/11 , H01L27/76
CPC分类号： H01L27/11 , H01L21/823878 , H01L27/1104
摘要： A 6-T SRAM cell having a MOS transistor with source/drain regions having an absence of heavily doped portions characteristic of prior art lightly doped drain (LDD) MOS devices is fabricated. Forming the MOS transistor with an absence of heavily doped portions of source/drain regions allows the width of the MOS gate layer, the width of the MOS source/drain regions and the width of the field oxide region between active regions of the SRAM cell to be reduced compared to the prior art. Accordingly, the present SRAM cell occupies less chip area than a prior art SRAM cell. Further, forming the MOS transistor without heavily doped portions of source/drain regions improves latch-up immunity and decreases write cycle time of the present SRAM cell.
摘要翻译：制造具有MOS晶体管的6-T SRAM单元，源极/漏极区域不存在现有技术的轻掺杂漏极（LDD）MOS器件的特征的重掺杂部分。在不存在源极/漏极区域的重掺杂部分的情况下形成MOS晶体管允许MOS栅极层的宽度，MOS源极/漏极区域的宽度以及SRAM单元的有源区域之间的场氧化物区域的宽度到与现有技术相比减少。因此，本SRAM单元占用比现有技术的SRAM单元小的芯片面积。此外，形成不具有源极/漏极区域的重掺杂部分的MOS晶体管改善了闩锁抗扰性并且减小了当前SRAM单元的写周期时间。

29. 发明授权

US5888861A Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow 失效
标题翻译：制造完全集成在CMOS工艺流程中的BiCMOS集成电路的方法
公开(公告)号：US5888861A
公开(公告)日：1999-03-30
申请号：US870474
申请日：1997-06-06
申请人： Chung-Jen Chien , Jeong Y. Choi , Chuen-Der Lien
发明人： Chung-Jen Chien , Jeong Y. Choi , Chuen-Der Lien
IPC分类号： H01L21/8249 , H01L21/8238
CPC分类号： H01L21/8249
摘要： A process for manufacturing a BiCMOS integrated circuit is implemented by adapting the masking and doping steps used in forming CMOS devices. Thus simultaneous formation of both CMOS and bipolar device structures eliminates the need for any additional masking or process steps to form bipolar device structures. Collector regions 20 of NPN transistors are formed simultaneously with N-wells 18. Collector regions of PNP transistors, if required, are formed simultaneously with P-wells 16. Base regions 24 of the bipolar transistors are formed using threshold voltage implant steps and/or lightly doped drain implant steps of PMOS transistors. Emitter regions 59 are formed, when using a single polysilicon CMOS process, simultaneously with the CMOS gates 72, 74. When employing a double polysilicon CMOS process, the emitter regions 59 are formed concurrently with the second polysilicon layer interconnect structure and/or source/drain regions 50,52 of NMOS transistors. For single polysilicon CMOS process, the buried layer regions 66 are formed during buried contact formation.
摘要翻译： BiCMOS集成电路的制造工艺通过适应用于形成CMOS器件的掩模和掺杂步骤来实现。因此同时形成CMOS和双极器件结构消除了对形成双极器件结构的任何附加掩模或工艺步骤的需要。 NPN晶体管的集电极区域20与N阱18同时形成。如果需要，PNP晶体管的集电极区域与P阱16同时形成。双极晶体管的基极区域24使用阈值电压注入步骤和/或 PMOS晶体管的轻掺杂漏极注入步骤。当使用单个多晶硅CMOS工艺时，发射极区59与CMOS栅极72,74同时形成。当采用双重多晶硅CMOS工艺时，发射极区59与第二多晶硅层互连结构和/或源/ NMOS晶体管的漏极区域50,52。对于单多晶硅CMOS工艺，在掩埋接触形成期间形成掩埋层区域66。

30. 发明授权

US5847429A Multiple node ESD devices 失效
标题翻译：多节点ESD器件
公开(公告)号：US5847429A
公开(公告)日：1998-12-08
申请号：US690021
申请日：1996-07-31
申请人： Chuen-Der Lien , Paul Y. M. Shy
发明人： Chuen-Der Lien , Paul Y. M. Shy
IPC分类号： H01L27/02 , H01L27/07 , H01L23/62
CPC分类号： H01L27/0248 , H01L27/0266 , H01L27/0705
摘要： An ESD protection device is provided which reduces the layout area required, utilizing multiple-node configurations and multiple node electrical couplings.
摘要翻译：提供了一种ESD保护装置，其减少了所需的布局面积，利用多节点配置和多节点电耦合。

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