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21. 发明申请

US20080282213A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 有权
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080282213A1
公开(公告)日：2008-11-13
申请号：US12181447
申请日：2008-07-29
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

22. 发明授权

US09524363B2 Element placement in circuit design based on preferred location 有权
标题翻译：基于优选位置的电路设计元素放置
公开(公告)号：US09524363B2
公开(公告)日：2016-12-20
申请号：US13485828
申请日：2012-05-31
申请人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Chin Ngai Sze , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5081
摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.
摘要翻译：改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

23. 发明申请

US20080066037A1 METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS 审中-公开
标题翻译：通过扩展力矢量调制降低分析放置技术的线性的方法
公开(公告)号：US20080066037A1
公开(公告)日：2008-03-13
申请号：US11531322
申请日：2006-09-13
申请人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of force directed placement programming is presented. The method includes sorting objects of a netlist for placement by magnitude of their spreading force and selecting a plurality of the objects. The method further includes waiving (or nullifying) the spreading force for the selected objects in a subsequent non-linear program solver step of the force directed placement program. The positions of the objects after the subsequent non-linear program solver step are based only on their connections to other objects in the netlist. The selected objects no longer retain their relative ordering as obtained during a previous non-linear program solve step of the force directed placement program. An alternative method of force directed placement programming is also present, which includes identifying objects from a netlist for placement that have a very high spreading force magnitude. The method further includes controlling the spreading force magnitude for the objects identified in the force directed placement programming to reduce wirelength in a chip design without sacrificing spreading of the objects.
摘要翻译：提出了一种强制定向布置程序的方法。该方法包括对网表的对象进行排序，以便按照其展开力的大小进行放置并选择多个对象。该方法还包括在力定向放置程序的随后非线性程序解算器步骤中放弃（或消除）所选对象的展开力。在后续非线性程序求解器步骤之后的对象的位置仅基于它们与网表中其他对象的连接。所选择的对象不再保留在力定向放置程序的先前非线性程序解决步骤中获得的相对排序。还存在一种替代的力定向放置编程的方法，其包括从具有非常高的铺展力量级的用于放置的网表识别对象。该方法还包括控制在力定向放置编程中识别的物体的展开力大小以减少芯片设计中的线长度，而不牺牲物体的扩展。

24. 发明申请

US20130086543A1 MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：集成电路设计中的多图形图形识别芯片布局
公开(公告)号：US20130086543A1
公开(公告)日：2013-04-04
申请号：US13248711
申请日：2011-09-29
申请人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
发明人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。执行细胞运动的全局阶段。执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位在为IC设计制作最终布局之前。

25. 发明授权

US08458634B2 Latch clustering with proximity to local clock buffers 失效
标题翻译：锁定聚类，靠近本地时钟缓冲区
公开(公告)号：US08458634B2
公开(公告)日：2013-06-04
申请号：US12912919
申请日：2010-10-27
申请人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/62
摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.
摘要翻译：一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。确定第一组多个群集锁存器中的多个组。添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

26. 发明申请

US20120110532A1 LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS 失效
标题翻译：对本地时钟缓冲器进行锁存的锁存器
公开(公告)号：US20120110532A1
公开(公告)日：2012-05-03
申请号：US12912919
申请日：2010-10-27
申请人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
发明人： Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , David Anthony Papa , Chin Ngai Sze , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/62
摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.
摘要翻译：一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。确定第一组多个群集锁存器中的多个组。添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

27. 发明授权

US08495548B2 Multi-patterning lithography aware cell placement in integrated circuit design 失效
标题翻译：集成电路设计中的多图案化光刻感知单元放置
公开(公告)号：US08495548B2
公开(公告)日：2013-07-23
申请号：US13248711
申请日：2011-09-29
申请人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
发明人： Kanak Behari Agarwal , Charles Jay Alpert , Zhuo Li , Gi-Joon Nam , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译：在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。执行细胞运动的全局阶段。执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位在为IC设计制作最终布局之前。

28. 发明授权

US08589848B2 Datapath placement using tiered assignment 有权
标题翻译： Datapath放置使用分层分配
公开(公告)号：US08589848B2
公开(公告)日：2013-11-19
申请号：US13451382
申请日：2012-04-19
申请人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.
摘要翻译：数据路径布局定义了单元格集群的布局集合的层次，将单元格分配给由数据路径宽度约束的层，然后在每个层中排序单元格。使用基于机器学习的数据路径提取来识别群集。数据路径宽度通过计算群集中的单元格的边界框的大小来确定。使用从集群的输入单元开始的宽度优先搜索来标识放置集。最初使用逻辑深度分配定义层次。可以通过从下一较高层拉动单元以填充空位或通过将多余单元推入下一较高层来将单元分配给层。根据线长成本函数，使用贪心小区分配在每个层中对单元进行排序。数据路径放置可以是迭代过程的一部分，其基于计算的拥塞信息将扩展约束应用于集群。

29. 发明申请

US20130283225A1 DATAPATH PLACEMENT USING TIERED ASSIGNMENT 有权
标题翻译：使用方式分配的DATAPATH放置
公开(公告)号：US20130283225A1
公开(公告)日：2013-10-24
申请号：US13451382
申请日：2012-04-19
申请人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.
摘要翻译：数据路径布局定义了单元格集群的布局集合的层次，将单元格分配给由数据路径宽度约束的层，然后在每个层中排序单元格。使用基于机器学习的数据路径提取来识别群集。数据路径宽度通过计算群集中的单元格的边界框的大小来确定。使用从集群的输入单元开始的宽度优先搜索来标识放置集。最初使用逻辑深度分配定义层次。可以通过从下一较高层拉动单元以填充空位或通过将多余单元推入下一较高层来将单元分配给层。根据线长成本函数，使用贪心小区分配在每个层中对单元进行排序。数据路径放置可以是迭代过程的一部分，其基于计算的拥塞信息将扩展约束应用于集群。

30. 发明申请

US20120266124A1 Placement of Structured Nets 有权
标题翻译：结构网的布置
公开(公告)号：US20120266124A1
公开(公告)日：2012-10-18
申请号：US13086428
申请日：2011-04-14
申请人： Charles J. Alpert , Myung-Chul Kim , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
发明人： Charles J. Alpert , Myung-Chul Kim , Zhuo Li , Natarajan Viswanathan , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells.
摘要翻译：提供了用于在半导体器件的设计中执行电池放置的机构。生成半导体器件的初始设计，初始设计包括单元的第一放置。确定与细胞相关联的放置的优选方向。优选的方向是细胞扩散优选的方向。基于与单元相关联的放置的优选方向，通过修改单元的第一放置以产生与第一放置单元不同的单元的第二放置来生成半导体器件的第二设计。

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