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21. 发明申请

US20090230776A1 INTEGRATED MULTI-TRANSFORMER 有权
标题翻译：集成多变压器
公开(公告)号：US20090230776A1
公开(公告)日：2009-09-17
申请号：US12404971
申请日：2009-03-16
申请人： Sam Seiichiro Ochi , Ernest Henry Wittenbreder, JR.
发明人： Sam Seiichiro Ochi , Ernest Henry Wittenbreder, JR.
IPC分类号： H02J4/00 , H01F27/34 , H01F41/06
CPC分类号： H01F19/00 , H01F27/38 , H01F30/12 , Y10T29/49071 , Y10T307/297 , Y10T307/713
摘要： Methods, systems, and devices are described for integrating multiple transformers on a shared core, while avoiding interference between the transformers and other potentially undesirable effects of the integration. In one embodiment, multiple transformers are wound on a shared core. Each transformer is wound on the core, so that its primary and secondary windings are magnetically coupled to each other through the core without being coupled to the windings of other transformers sharing the core. The multiple integrated transformers may then be provided in a circuit arrangement by placing only a single core element in the arrangement.
摘要翻译：描述了用于在共享内核上集成多个变压器的方法，系统和设备，同时避免变压器之间的干扰和集成的其他潜在的不良影响。在一个实施例中，多个变压器缠绕在共享芯上。每个变压器被缠绕在芯上，使得其初级和次级绕组通过芯彼此磁耦合，而不耦合到共享芯的其它变压器的绕组。然后可以通过在该布置中放置单个芯元件来以电路布置来提供多个集成变压器。

22. 发明授权

US07449896B2 Current sensor using level shift circuit 有权
标题翻译：电流传感器使用电平移位电路
公开(公告)号：US07449896B2
公开(公告)日：2008-11-11
申请号：US11496981
申请日：2006-07-31
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： G01R27/08
CPC分类号： H03F3/45475 , G01R19/0092 , H03F3/345 , H03F2200/261 , H03F2200/462 , H03F2203/45581
摘要： A circuit for sensing a current includes a first upper resistor having a first end coupled to a first end of a sense resistor, the sense resistor being configured to receive an input current. A second upper resistor has a first end coupled to a second end of the sense resistor, so that the sense resistor defines a first potential between the first and second ends of the sense resistor. A first lower resistor is provided between the first upper resistor and the ground. A second lower resistor is provided between the second upper resistor and the ground. An amplifier has a first input node and a second input node, the first input node being coupled to a node between the first upper resistor and the first lower resistor. The second input node is coupled to a node between the to the second upper resistor and the second lower resistor. The first and second input nodes defines a second potential corresponding to the first potential.
摘要翻译：用于感测电流的电路包括具有耦合到检测电阻器的第一端的第一端的第一上电阻器，感测电阻器被配置为接收输入电流。第二上电阻器具有耦合到检测电阻器的第二端的第一端，使得检测电阻器在感测电阻器的第一端和第二端之间限定第一电位。在第一上电阻器和地之间提供第一下电阻器。在第二上电阻器和地之间提供第二下电阻器。放大器具有第一输入节点和第二输入节点，第一输入节点耦合到第一上电阻器和第一下电阻器之间的节点。第二输入节点耦合到第二上电阻器和第二下电阻器之间的节点。第一和第二输入节点定义对应于第一电位的第二电位。

23. 发明授权

US06917227B1 Efficient gate driver for power device 有权
标题翻译：电源设备高效栅极驱动器
公开(公告)号：US06917227B1
公开(公告)日：2005-07-12
申请号：US10136844
申请日：2002-04-30
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： H03K17/082 , H03K17/16 , H03K3/00
CPC分类号： H03K17/163 , H03K17/0822
摘要： A power module includes a power semiconductor device having a first terminal, a second terminal, and a third terminal. The second terminal is a control terminal to regulate flow of electricity between the first and third terminals. A gate driver has an output node coupled to the second terminal of the power device. The gate driver includes an upper transistor and a lower transistor provided in a half-bridge configuration. The output node of the gate driver is provided between the upper and lower transistors. A first delay circuit is coupled to a control terminal of the upper transistor to provide a first delay period for a first gate drive signal being applied to the control terminal of the upper transistor. A second delay circuit is coupled to a control terminal of the lower transistor to provide a second delay period for a second gate drive signal being applied to the control terminal the lower transistor. The first delay period is different from the second delay period.
摘要翻译：功率模块包括具有第一端子，第二端子和第三端子的功率半导体器件。第二端子是用于调节第一和第三端子之间的电流的控制端子。栅极驱动器具有耦合到功率器件的第二端子的输出节点。栅极驱动器包括设置在半桥配置中的上晶体管和下晶体管。栅极驱动器的输出节点设置在上部和下部晶体管之间。第一延迟电路耦合到上部晶体管的控制端子，以提供施加到上部晶体管的控制端子的第一栅极驱动信号的第一延迟周期。第二延迟电路耦合到下部晶体管的控制端子，以向第二栅极驱动信号提供第二延迟周期，第二延迟周期施加到控制端子的下部晶体管。第一延迟周期与第二延迟周期不同。

24. 发明授权

US06759692B1 Gate driver with level shift circuit 有权
标题翻译：门驱动器与电平移位电路
公开(公告)号：US06759692B1
公开(公告)日：2004-07-06
申请号：US10349804
申请日：2003-01-22
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： H01L2974
CPC分类号： H01L23/5222 , H01L23/5228 , H01L24/05 , H01L27/0676 , H01L27/0682 , H01L27/0805 , H01L2224/04042 , H01L2224/05093 , H01L2224/05554 , H01L2224/05556 , H01L2224/4813 , H01L2224/48463 , H01L2224/48464 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H02M1/08 , H02M1/088 , H03K17/063 , H03K17/162 , H01L2924/00
摘要： A gate driver includes a gate control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch and a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay.
摘要翻译：栅极驱动器包括具有第一输入并被配置为向功率半导体开关输出栅极控制信号的门控制信号发生器和具有适于发送信号的第一信号路径和第二信号路径的第一子电路。第一和第二信号路径耦合到门控制信号发生器的第一输入端。第二信号路径被配置为以减小的信号延迟向第一输入提供信号。

25. 发明授权

US06638808B1 Method of manufacturing gate driver with level shift circuit 有权
标题翻译：具有电平移位电路的栅极驱动器制造方法
公开(公告)号：US06638808B1
公开(公告)日：2003-10-28
申请号：US10353722
申请日：2003-01-28
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： H01L218234
CPC分类号： H01L27/0805 , H01L23/5222 , H01L23/5228 , H01L24/05 , H01L27/0676 , H01L27/0682 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/4813 , H01L2224/48463 , H01L2224/48464 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H02M1/08 , H03K17/063 , H01L2924/00
摘要： A method for forming a gate driver configured to drive a power semiconductor device includes providing a substrate having an upper surface; forming a conductive region on a portion of the upper surface of the substrate; forming a dielectric layer overlying the conductive region; forming a first conductive layer provided over the conductive region and at least a portion of the dielectric layer; patterning the first conductive layer to provide the first conductive layer with a given resistance value; forming a second conductive layer over the dielectric layer and electrically coupled to the conductive region and first conductive layer; and patterning the second conductive layer to provide an input node that is coupled to a first portion of the resistor and an output node that is coupled to a second portion of the resistor. The input node is configured to receive a control signal from a control signal generator and the output node is configured to receive the control signal from the input node via the resistor. The conductive region, the first conductive layer, and the at least portion of the dielectric layer together form a first capacitor.
摘要翻译：一种形成驱动功率半导体器件的栅极驱动器的方法包括：提供具有上表面的衬底; 在所述基板的上表面的一部分上形成导电区域; 形成覆盖所述导电区域的介电层; 形成设置在导电区域和电介质层的至少一部分上的第一导电层; 图案化第一导电层以向第一导电层提供给定的电阻值; 在所述电介质层上形成第二导电层，并电耦合到所述导电区域和所述第一导电层; 以及图案化所述第二导电层以提供耦合到所述电阻器的第一部分的输入节点和耦合到所述电阻器的第二部分的输出节点。输入节点被配置为从控制信号发生器接收控制信号，并且输出节点被配置为经由电阻器从输入节点接收控制信号。导电区域，第一导电层和介电层的至少部分一起形成第一电容器。

26. 发明申请

US20090295228A1 POWER SUPPLY WITH STANDBY POWER 有权
标题翻译：电源供电
公开(公告)号：US20090295228A1
公开(公告)日：2009-12-03
申请号：US12472539
申请日：2009-05-27
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： H02J9/00
CPC分类号： H02M3/156 , H02M2001/0032 , Y02B70/16 , Y10T307/625 , Y10T307/76
摘要： Methods, systems, and devices are described for auxiliary power with low standby power consumption. Switching power converters typically include a switching power element (e.g., a power transistor), driven by a switching controller (e.g., including a gate driver). The power output of the switching power converter may be a function of the switching signal provided by the switching controller. For example, a pulse-width modulated (“PWM”) signal may be used to drive the switching power element, and the output of the switching controller may be adjusted by adjusting the frequency and/or duty cycle of the PWM signal. Embodiments implement cycle extension techniques to effectively extend a portion of the PWM signal to generate additional charge. The additional charge may be used to power an auxiliary power unit. The auxiliary power unit may then be used to drive the switching controller and/or to provide a source of power for other internal or external components.
摘要翻译：描述了具有低待机功耗的辅助电源的方法，系统和设备。开关电源转换器通常包括由开关控制器（例如，包括栅极驱动器）驱动的开关功率元件（例如，功率晶体管）。开关功率转换器的功率输出可以是由开关控制器提供的开关信号的函数。例如，可以使用脉冲宽度调制（“PWM”）信号来驱动开关功率元件，并且可以通过调整PWM信号的频率和/或占空比来调节开关控制器的输出。实施例实现循环扩展技术以有效地扩展PWM信号的一部分以产生附加电荷。附加电荷可用于为辅助电源单元供电。然后可以使用辅助动力单元来驱动开关控制器和/或为其他内部或外部组件提供电源。

27. 发明申请

US20090256617A1 VOLTAGE LEVEL SHIFTER 有权
标题翻译：电压水平变换器
公开(公告)号：US20090256617A1
公开(公告)日：2009-10-15
申请号：US12422060
申请日：2009-04-10
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： H03L5/00
CPC分类号： H03K19/018564 , H03F3/2173 , H03F2200/291 , H03K17/6874
摘要： Methods, systems, and devices are described for providing voltage level shifting that may operate reliably and at low power, even at high voltages and/or high switching frequencies. Embodiments receive an input signal representing input information, and effectively generate two voltage responses as a function of the input signal. Each voltage response includes exponential terms as a function of resistive and capacitive loading effects of components of the embodiments. A combined response signal is generated substantially as a superposition of the first response signal and the second response signal. A high-side driver signal is then generated as a function of the combined response signal, such that the high-side driver signal substantially preserves the input information represented by the input signal, and such that the first exponential response and the second exponential response are substantially absent from the high-side driver signal.
摘要翻译：描述了用于提供即使在高电压和/或高开关频率下可靠且低功率运行的电压电平转换的方法，系统和装置。实施例接收表示输入信息的输入信号，并有效地产生作为输入信号的函数的两个电压响应。每个电压响应包括指数项作为实施例的组件的电阻和电容负载效应的函数。基本上产生组合响应信号作为第一响应信号和第二响应信号的叠加。然后，根据组合的响应信号产生高侧驱动器信号，使得高侧驱动器信号基本上保留由输入信号表示的输入信息，并且使得第一指数响应和第二指数响应为基本上不存在高侧驾驶员信号。

28. 发明授权

US06771478B2 Hot-swap protection circuit 有权
标题翻译：热插拔保护电路
公开(公告)号：US06771478B2
公开(公告)日：2004-08-03
申请号：US10029593
申请日：2001-12-21
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： H02H106
CPC分类号： H02H9/004 , H03K17/0822 , H03K17/163
摘要： Embodiments of the present invention provide methods and circuitry for protecting a circuit during hot-swap events. Hot swap protection circuitry includes as overcurrent detection circuit which decouples power from a load. Circuitry is provided to detect ground-fault conditions. Noise detection circuitry is provided to reduce noise in the power that is delivered to the load.
摘要翻译：本发明的实施例提供了用于在热插拔事件期间保护电路的方法和电路。热插拔保护电路包括作为使负载断电的过电流检测电路。提供电路以检测接地故障状况。提供噪声检测电路以减少输送到负载的电力中的噪声。

29. 发明授权

US5731729A Voltage transient suppression circuit for preventing overvoltages in power transistor systems 失效
标题翻译：用于防止功率晶体管系统过电压的电压瞬变抑制电路
公开(公告)号：US5731729A
公开(公告)日：1998-03-24
申请号：US372748
申请日：1995-01-13
申请人： Sam Seiichiro Ochi
发明人： Sam Seiichiro Ochi
IPC分类号： H01L27/02 , H03K17/082 , H03K17/08 , H03K17/56
CPC分类号： H01L27/0251 , H03K17/082
摘要： An apparatus for suppressing voltage transients across a first transistor is described. The first transistor has a first terminal, a second terminal, and a gate terminal, and is characterized by an avalanche breakdown voltage rating between the first and second terminals. The cathode of a first diode is coupled to the first terminal, the first diode having a reverse breakdown voltage which is less than the avalanche breakdown voltage rating. Gate driver circuitry is provided by which the gate terminal of the first transistor is coupled to the anode of the first diode. The gate driver circuitry provides a drive signal to the gate terminal of the first transistor, and comprises a plurality of bipolar transistors. Each bipolar transistor has an anode terminal (i.e., base terminal), a p-n junction, and a cathode terminal (i.e., emitter terminal). The anode terminal of each bipolar transistor is coupled to the anode of the first diode.
摘要翻译：描述了一种用于抑制跨越第一晶体管的电压瞬变的装置。第一晶体管具有第一端子，第二端子和栅极端子，其特征在于第一和第二端子之间的雪崩击穿电压额定值。第一二极管的阴极耦合到第一端子，第一二极管具有小于雪崩击穿电压额定值的反向击穿电压。栅极驱动器电路被提供，第一晶体管的栅极端子连接到第一二极管的阳极。栅极驱动器电路向第一晶体管的栅极端提供驱动信号，并且包括多个双极晶体管。每个双极晶体管具有阳极端子（即，基极端子），p-n结和阴极端子（即，发射极端子）。每个双极晶体管的阳极端子耦合到第一二极管的阳极。

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