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21. 发明授权

US07872852B2 Conductive structure having capacitor 有权
标题翻译：具有电容器的导电结构
公开(公告)号：US07872852B2
公开(公告)日：2011-01-18
申请号：US12029472
申请日：2008-02-12
申请人： Tsuoe-Hsiang Liao , Huo-Tieh Lu , Chih-Chien Liu , Hsiang-Hung Peng , Yu-Fang Chien
发明人： Tsuoe-Hsiang Liao , Huo-Tieh Lu , Chih-Chien Liu , Hsiang-Hung Peng , Yu-Fang Chien
IPC分类号： H01G4/005 , H01G4/06
CPC分类号： H01L23/5223 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional conductive structure has a first electrode and a second electrode of a capacitor structure, and thereby defines a capacitor space. At least a signal line is further included in the capacitor space where both the first electrode and the second electrode can cross and detour round the signal line. Therefore, the signal line can go directly through the capacitor space for transferring various signals without making a detour to avoid the whole capacitor structure.
摘要翻译：三维导电结构具有电容器结构的第一电极和第二电极，从而限定电容器空间。至少一个信号线还包括在电容器空间中，其中第一电极和第二电极都可以跨越信号线并绕道。因此，信号线可以直接通过电容器空间传输各种信号，而不会绕行，以避免整个电容器结构。

22. 发明申请

US20100173490A1 HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESS 有权
标题翻译：高密度等离子体化学气相沉积工艺
公开(公告)号：US20100173490A1
公开(公告)日：2010-07-08
申请号：US12729234
申请日：2010-03-22
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/768
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

23. 发明授权

US07718079B2 High density plasma chemical vapor deposition process 有权
标题翻译：高密度等离子体化学气相沉积工艺
公开(公告)号：US07718079B2
公开(公告)日：2010-05-18
申请号：US09991196
申请日：2001-11-20
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/467 , H01L21/32 , H01L21/308 , H01L21/762
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

24. 发明申请

US20090261419A1 SEMICONDUCTOR DEVICE HAVING ASSIST FEATURES AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有辅助功能的半导体器件及其制造方法
公开(公告)号：US20090261419A1
公开(公告)日：2009-10-22
申请号：US12107077
申请日：2008-04-22
申请人： Shu-Ping Fang , Tien-Cheng Lan , Chih-Chien Liu
发明人： Shu-Ping Fang , Tien-Cheng Lan , Chih-Chien Liu
IPC分类号： H01L29/78 , H01L21/76 , G03F7/20
CPC分类号： H01L27/0207
摘要： A semiconductor device having assist features and manufacturing method thereof includes a substrate having at least an active region and a peripheral region defined thereon. The semiconductor device also includes a plurality of assist features positioned in the peripheral region, or in the active region with a dotted line pattern. The assist features are electrically connected to active circuits formed in the active region, respectively, for serving as redundant circuits that repair or replace defective circuits.
摘要翻译：具有辅助特征的半导体器件及其制造方法包括至少具有限定在其上的有源区和周边区的衬底。半导体器件还包括位于外围区域中的多个辅助特征，或者在有源区域中具有虚线图案。辅助特征分别电连接到形成在有源区域中的有源电路，用作修复或替换有缺陷电路的冗余电路。

25. 发明授权

US07514014B1 High density plasma chemical vapor deposition process 有权
公开(公告)号：US07514014B1
公开(公告)日：2009-04-07
申请号：US09546174
申请日：2000-04-11
申请人： Chih-Chien Liu , Ta-Shan Tseng , W. B. Shieh , J. Y. Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , W. B. Shieh , J. Y. Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/467 , H01L21/32 , H01L21/308 , H01L21/762
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

26. 发明授权

US07439154B2 Method of fabricating interconnect structure 有权
标题翻译：制造互连结构的方法
公开(公告)号：US07439154B2
公开(公告)日：2008-10-21
申请号：US11565632
申请日：2006-12-01
申请人： Feng-Yu Hsu , Chih-Chien Liu , Jim-Jey Huang , Jei-Ming Chen
发明人： Feng-Yu Hsu , Chih-Chien Liu , Jim-Jey Huang , Jei-Ming Chen
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L23/53295 , H01L21/7682 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating an interconnect structure is described. A substrate with a conductive part thereon is provided, a first porous low-k layer is formed on the substrate, and then a first UV-curing step is conducted. A damascene structure is formed in the first porous low-k layer to electrically connect with the conductive part, and then a first UV-absorption layer is formed on the first porous low-k layer and the damascene structure. A second porous low-k layer is formed on the first UV-absorption layer, and a second UV-curing step is conducted.
摘要翻译：描述了制造互连结构的方法。提供其上具有导电部分的基板，在基板上形成第一多孔低k层，然后进行第一UV固化步骤。在第一多孔低k层中形成镶嵌结构以与导电部分电连接，然后在第一多孔低k层和镶嵌结构上形成第一紫外线吸收层。在第一UV吸收层上形成第二多孔低k层，进行第二UV固化步骤。

27. 发明授权

US07271101B2 High density plasma chemical vapor deposition process 有权
标题翻译：高密度等离子体化学气相沉积工艺
公开(公告)号：US07271101B2
公开(公告)日：2007-09-18
申请号：US11315904
申请日：2005-12-22
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/311
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

28. 发明授权

US06750129B2 Process for forming fusible links 有权
标题翻译：形成易熔连接的工艺
公开(公告)号：US06750129B2
公开(公告)日：2004-06-15
申请号：US10292399
申请日：2002-11-12
申请人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
发明人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
摘要翻译：一种用于在集成电路中形成可熔链节的方法，其中可熔链在最终金属化层中与焊盘同时形成。该方法可以应用于采用铜金属化和低k电介质材料的集成电路的制造中。在对最终的金属（铝）层进行构图以形成可熔连接件和接合焊盘之后，在沉积钝化层之前，在最终的金属层上形成介电蚀刻停止层。钝化层在可熔接头和接合焊盘上的区域中被去除。电介质蚀刻停止层仅从接合焊盘上方或者从焊盘和可熔连接部上方移除。

29. 发明授权

US5976984A Process of making unlanded vias 失效
标题翻译：制作无人化过孔的过程
公开(公告)号：US5976984A
公开(公告)日：1999-11-02
申请号：US1416
申请日：1997-12-30
申请人： Coming Chen , Chih-Chien Liu , Kun-Chih Wang , Tri-Rung Yew
发明人： Coming Chen , Chih-Chien Liu , Kun-Chih Wang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L23/522 , H01L21/02
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76829 , H01L2924/0002
摘要： A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.
摘要翻译：公开了一种在半导体IC器件中形成通孔的方法，该半导体IC器件具有与互连表面的充分接触并且没有不足够的着陆。该方法具有形成在IC器件的衬底上的金属层中的互连，并且覆盖互连表面的第一介电层被形成。然后在第一介电层的顶部上形成蚀刻停止层，随后在蚀刻停止层的顶部形成第二电介质层。光致抗蚀剂层然后覆盖第二电介质层并且显露指定用于形成通孔的第二电介质层的表面区域。然后执行主蚀刻程序以蚀刻到第二介电层中，直到蚀刻停止层的表面，从而形成通孔的第一部分。然后实施过蚀刻程序以剥离蚀刻停止层并进一步蚀刻到第一介电层中，然后当显露互连表面以终止形成通孔时，停止蚀刻。

30. 发明申请

US20190305414A1 COMMUNICATION APPARATUS, ELECTRONIC APPARATUS AND ANTENNA ADJUSTMENT METHOD 审中-公开
公开(公告)号：US20190305414A1
公开(公告)日：2019-10-03
申请号：US16372412
申请日：2019-04-02
申请人： Liang-Che Chou , Li-Chun Lee , Yu-Chun Hsieh , Mau-Chi Sun , Jui-Hung Lai , Wen-Feng Tsai , Chih-Chien Liu
发明人： Liang-Che Chou , Li-Chun Lee , Yu-Chun Hsieh , Mau-Chi Sun , Jui-Hung Lai , Wen-Feng Tsai , Chih-Chien Liu
IPC分类号： H01Q1/52 , H01Q1/24 , H04B1/18
摘要： A communication apparatus, an electronic apparatus and an antenna adjustment method thereof are provided. The communication apparatus includes an antenna system, a tuning portion and a switch circuit. The antenna system includes at least two antenna units. The tuning portion is disposed between the at least two antenna units and includes at least two branch units. The switch circuit is coupled to the tuning portion. The switch circuit switches a conduction from a first one of the branch units to a second one of the branch units according to a switching signal. The switching signal is related to performances of the antenna system. Accordingly, a dynamic and flexible adjustment mechanism can be provided to increase throughput and improve users' internet experience.

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