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21. 发明授权

US07052622B2 Method for measuring etch rates during a release process 失效
公开(公告)号：US07052622B2
公开(公告)日：2006-05-30
申请号：US10265620
申请日：2002-10-08
申请人： Jeffrey D. Chinn , Robert Z. Bachrach
发明人： Jeffrey D. Chinn , Robert Z. Bachrach
IPC分类号： C03C15/00
CPC分类号： B81C1/00476 , B81C99/0065 , B81C2201/0142
摘要： A method of determining the time to release of a movable feature in a multilayer substrate of silicon-containing materials including alternate layers of polysilicon and silicon oxide wherein a mass monitoring device determines the mass of a released feature, and the substrate is etched with anhydrous hydrogen fluoride until the substrate mass is equivalent to that of the released movable feature when the etch time is noted. A suitable mass monitoring device is a quartz crystal microbalance.

22. 发明授权

US5223443A Method for determining wafer cleanliness 失效
标题翻译：确定晶片清洁度的方法
公开(公告)号：US5223443A
公开(公告)日：1993-06-29
申请号：US838539
申请日：1992-02-19
申请人： Jeffrey D. Chinn , Ciaran P. Hanrahan
发明人： Jeffrey D. Chinn , Ciaran P. Hanrahan
IPC分类号： H01L21/306
CPC分类号： H01L21/02052
摘要： An embodiment of the present invention is a method for determining the cleanliness of a semiconductor wafer initially deposited with polysilicon, patterned with photoresist, processed, and then having the resist removed under standard conditions. The method comprising the steps of: depositing a thin TEOS film over the entire surface of a wafer; exposing said wafer to a solution of hot potassium hydroxide (KOH) that attacks polysilicon and is highly selective to and does not etch said TEOS film, the exposing such that if any pin hole exists in the TEOS film an underlying layer of polysilicon is attacked vigorously; and inspecting said wafer for a visual indication in said polysilicon layer of whether or not said polysilicon layer was attacked by the exposure to said potassium hydroxide (KOH).
摘要翻译：本发明的一个实施例是用于确定最初沉积多晶硅的半导体晶片的清洁度的方法，用光刻胶图案化，加工，然后在标准条件下除去抗蚀剂。该方法包括以下步骤：在晶片的整个表面上沉积薄的TEOS膜; 将所述晶片暴露于攻击多晶硅的热氢氧化钾（KOH）的溶液中，并且对TEOS膜具有高度选择性且不蚀刻所述TEOS膜，所述曝光使得如果在TEOS膜中存在任何针孔，则下层的多晶硅被剧烈地侵蚀 ; 以及在所述多晶硅层中检查所述晶片的视觉指示，判断所述多晶硅层是否暴露于所述氢氧化钾（KOH）中。

23. 发明授权

US5117276A High performance interconnect system for an integrated circuit 失效
标题翻译：用于集成电路的高性能互连系统
公开(公告)号：US5117276A
公开(公告)日：1992-05-26
申请号：US610962
申请日：1990-11-08
申请人： Michael E. Thomas , Jeffrey D. Chinn
发明人： Michael E. Thomas , Jeffrey D. Chinn
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/64
CPC分类号： H01L21/76879 , H01L21/76801 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76843 , H01L21/76852 , H01L23/5221 , H01L23/5226 , H01L23/53223 , H01L23/642 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.
摘要翻译：半导体集成电路器件包括高性能互连结构，其包括多个互连，每个互连在结构上与除了电接触点之外的其余互连分开。在一个实施例中，每个互连基本上被介电材料层包围，每个邻近的介电材料层之间存在间隙。另一个实施例中，导电材料层形成在周围的电介质层上，优选地填充在相邻的介电材料层之间的间隙中。导电材料层用作接地平面和散热片。

24. 发明授权

US08071160B2 Surface coating process 有权
标题翻译：表面涂层工艺
公开(公告)号：US08071160B2
公开(公告)日：2011-12-06
申请号：US12115874
申请日：2008-05-06
申请人： Jeffrey D. Chinn , Robert W. Ashurst , Adam N. Anderson
发明人： Jeffrey D. Chinn , Robert W. Ashurst , Adam N. Anderson
IPC分类号： B05D5/12 , H05K3/00 , C23C16/00
CPC分类号： H05K3/284 , H01L23/49894 , H01L2924/0002 , H05K2201/0209 , H05K2201/0239 , H05K2201/0257 , H05K2201/09872 , Y10T428/24355 , Y10T428/24364 , Y10T428/24372 , Y10T428/24388 , Y10T428/24405 , Y10T428/24413 , Y10T428/24421 , Y10T428/269 , Y10T428/2839 , H01L2924/00
摘要： A method of forming a film is provided. Nanoparticles are deposited on a surface of a substrate using a liquid deposition process. The nanoparticles are linked to each other and to the surface using linker molecules. A coating having a surface energy of less than 70 dyne/cm is deposited over the film to form a coated film. The coated film has an RMS surface roughness of 25 nm to 500 nm, a film coverage of 25% to 60%, a surface energy of less than 70 dyne/cm; and a durability of 10 to 5000 microNewtons. Depending on the particular environment in which the film is to be used, a durability of 10 to 500 microNewtons may be preferred. A film thickness 3 to 100 times the RMS surface roughness of the film is preferred.
摘要翻译：提供了一种形成膜的方法。使用液体沉积工艺将纳米颗粒沉积在基底的表面上。使用接头分子将纳米颗粒彼此连接并连接到表面。表面能小于70达因/厘米的涂层沉积在膜上以形成涂膜。涂膜的RMS表面粗糙度为25nm至500nm，膜覆盖率为25％至60％，表面能小于70达因/厘米; 耐久性为10至5000微瓦。根据使用薄膜的具体环境，可以优选10至500微瓦的耐久性。膜的厚度为膜的RMS表面粗糙度的3〜100倍是优选的。

25. 发明授权

US07776396B2 Controlled vapor deposition of multilayered coatings adhered by an oxide layer 有权
公开(公告)号：US07776396B2
公开(公告)日：2010-08-17
申请号：US11112664
申请日：2005-04-21
申请人： Boris Kobrin , Jeffrey D. Chinn , Romuald Nowak , Richard C. Yi
发明人： Boris Kobrin , Jeffrey D. Chinn , Romuald Nowak , Richard C. Yi
IPC分类号： C23C16/40
CPC分类号： C23C16/0227 , B05D1/185 , B05D1/60 , B05D3/142 , B05D3/145 , B05D7/52 , B05D7/56 , B82Y30/00 , B82Y40/00 , C03C17/42 , C03C23/006 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/402 , C23C16/448 , C23C16/4485 , C23C16/455 , C23C16/45557 , C23C16/56 , Y10T428/12618 , Y10T428/12632 , Y10T428/24 , Y10T428/24355 , Y10T428/24967 , Y10T428/24975 , Y10T428/261 , Y10T428/265 , Y10T428/31663 , Y10T428/31667
摘要： An improved vapor-phase deposition method and apparatus for the application of multilayered films/coatings on substrates is described. The method is used to deposit multilayered coatings where the thickness of an oxide-based layer in direct contact with a substrate is controlled as a function of the chemical composition of the substrate, whereby a subsequently deposited layer bonds better to the oxide-based layer. The improved method is used to deposit multilayered coatings where an oxide-based layer is deposited directly over a substrate and an organic-based layer is directly deposited over the oxide-based layer. Typically, a series of alternating layers of oxide-based layer and organic-based layer are applied.

26. 发明授权

US07413774B2 Method for controlled application of reactive vapors to produce thin films and coatings 有权
标题翻译：用于控制应用反应蒸气以产生薄膜和涂层的方法
公开(公告)号：US07413774B2
公开(公告)日：2008-08-19
申请号：US11018173
申请日：2004-12-21
申请人： Boris Kobrin , Romuald Nowak , Richard C. Yi , Jeffrey D. Chinn
发明人： Boris Kobrin , Romuald Nowak , Richard C. Yi , Jeffrey D. Chinn
IPC分类号： C23C16/00
CPC分类号： B82Y30/00 , B05D1/185 , B05D1/60 , B05D3/142 , B82Y40/00 , C09D4/00 , C23C16/4485 , C08G77/04
摘要： A vapor phase deposition method and apparatus for the application of thin layers and coatings on substrates. The method and apparatus are useful in the fabrication of electronic devices, micro-electromechanical systems (MEMS), Bio-MEMS devices, micro and nano imprinting lithography, and microfluidic devices. The apparatus used to carry out the method provides for the addition of a precise amount of each of the reactants to be consumed in a single reaction step of the coating formation process. The apparatus provides for precise addition of quantities of different combinations of reactants during a single step or when there are a number of different individual steps in the coating formation process. The precise addition of each of the reactants in vapor form is metered into a predetermined set volume at a specified temperature to a specified pressure, to provide a highly accurate amount of reactant.
摘要翻译：一种用于在基底上施加薄层和涂层的气相沉积方法和装置。该方法和装置可用于制造电子设备，微机电系统（MEMS），生物MEMS装置，微型和纳米压印光刻以及微流体装置。用于实施该方法的装置提供了在涂层形成过程的单个反应步骤中添加精确量的每种待消耗的反应物。该装置提供在单一步骤期间或当涂层形成过程中存在许多不同的单独步骤时精确添加量的不同组合的反应物。将蒸气形式的每种反应物的精确加入在指定温度下计量到预定设定体积至指定压力，以提供高精度的反应物。

27. 发明申请

US20070281492A1 Protective thin films for use during fabrication of semiconductors, MEMS, and microstructures 有权
标题翻译：用于制造半导体，MEMS和微结构的保护薄膜
公开(公告)号：US20070281492A1
公开(公告)日：2007-12-06
申请号：US11447186
申请日：2006-06-05
申请人： Jeffrey D. Chinn , Boris Kobrin , Romuald Nowak
发明人： Jeffrey D. Chinn , Boris Kobrin , Romuald Nowak
IPC分类号： H01L21/47
CPC分类号： H01L21/02126 , B81C1/00896 , B81C2201/053 , C23C16/44 , C23C16/455 , H01L21/02263 , H01L21/3121
摘要： A method of protecting a substrate during fabrication of semiconductor, MEMS, or biotechnology devices. The method includes application of a protective thin film which typically has a thickness ranging from about 3 Å to about 1,000 Å, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.
摘要翻译：一种在制造半导体，MEMS或生物技术设备期间保护衬底的方法。该方法包括施加通常具有约3至约1000的厚度的保护性薄膜，其中用于沉积保护性薄膜的前体材料是有机基前体，其包括至少一个含氟官能团碳骨架的一端和在碳骨架的相对端处的至少一个功能键合基团，其中碳骨架的长度为4个碳到约12个碳原子。在许多应用中，在制造器件期间，保护薄膜的至少一部分被去除。

28. 发明授权

US06936183B2 Etch process for etching microstructures 失效
标题翻译：用于蚀刻微结构的蚀刻工艺
公开(公告)号：US06936183B2
公开(公告)日：2005-08-30
申请号：US10265598
申请日：2002-10-08
申请人： Jeffrey D. Chinn , Sofiane Soukane
发明人： Jeffrey D. Chinn , Sofiane Soukane
IPC分类号： B81B3/00 , G02B6/12 , G02B6/122 , G02B6/36 , C03C15/00
CPC分类号： B81C1/00928 , B81C2201/112 , G02B6/122 , G02B6/3692 , G02B2006/12176
摘要： A two-step method of releasing microelectromechanical devices from a substrate is disclosed. The first step comprises isotropically etching a silicon oxide layer sandwiched between two silicon-containing layers with a gaseous hydrogen fluoride-water mixture, the overlying silicon layer to be separated from the underlying silicon layer or substrate for a time sufficient to form an opening but not to release the overlying layer, and the second step comprises adding a drying agent to substitute for moisture remaining in the opening and to dissolve away any residues in the opening that can cause stiction.
摘要翻译：公开了一种从基板释放微机电装置的两步法。第一步包括用夹杂在两个含硅层之间的氧化硅层与氟化氢 - 水气体混合物进行各向同性蚀刻，所述上层硅层将从底层硅层或衬底分离足以形成开口但不以释放上覆层，第二步骤包括加入干燥剂以代替残留在开口中的水分，并溶解开口中可能导致静电的残留物。

29. 发明授权

US06902947B2 Integrated method for release and passivation of MEMS structures 失效
标题翻译： MEMS结构的释放和钝化的集成方法
公开(公告)号：US06902947B2
公开(公告)日：2005-06-07
申请号：US10435757
申请日：2003-05-09
申请人： Jeffrey D. Chinn , Rolf A. Guenther , Michael B. Rattner , James A. Cooper , Toi Yue Becky Leung , Claes H. Bjorkman
发明人： Jeffrey D. Chinn , Rolf A. Guenther , Michael B. Rattner , James A. Cooper , Toi Yue Becky Leung , Claes H. Bjorkman
IPC分类号： B81B3/00 , B81C1/00 , H01L21/00
CPC分类号： B81C1/0096 , B81B3/0005 , B81C2201/0176 , B81C2201/112 , B82Y30/00
摘要： Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises treating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures which may be adjusted to be carried out in a either a single chamber processing system or a multi-chamber processing system.
摘要翻译：本文公开了一种改进疏水性自组装单层（SAM）涂层到MEMS结构表面的粘附性的方法，以防止粘结。该方法包括用包含氧气和任选的氢气的源气体产生的等离子体处理MEMS结构的表面。处理氧化表面，然后与氢气反应以在表面上形成键合的OH基团。氢源可以作为等离子体源气体的一部分存在，使得在用等离子体处理表面期间产生结合的OH基团。本文还公开了一种用于MEMS结构的释放和钝化的集成方法，其可以被调整为在单室处理系统或多室处理系统中进行。

30. 发明授权

US06849554B2 Method of etching a deep trench having a tapered profile in silicon 失效
标题翻译：在硅中蚀刻具有锥形轮廓的深沟槽的方法
公开(公告)号：US06849554B2
公开(公告)日：2005-02-01
申请号：US10137176
申请日：2002-05-01
申请人： Michael Rattner , Jeffrey D. Chinn
发明人： Michael Rattner , Jeffrey D. Chinn
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/302
CPC分类号： H01L21/3065 , H01L21/76232
摘要： Disclosed herein is a method of etching deep trenches in a substrate which utilizes the overlying mask structure to achieve a trench having a positive tapered sidewall angle of less than about 88°. The method employs the successive etching of a lateral undercut in the substrate beneath a masking material, while at the same time etching vertically downward beneath the mask. The coordinated widening of the lateral undercut at the top of the trench, while vertically extending the depth of the trench, is designed to provide the desired trench sidewall taper angle.
摘要翻译：本文公开了一种蚀刻衬底中的深沟槽的方法，其利用上覆掩模结构来实现具有小于约88°的正锥形侧壁角的沟槽。该方法采用在掩模材料下面的衬底中的横向底切的连续蚀刻，同时在掩模下垂直向下蚀刻。在沟槽顶部的横向底切的协调加宽，同时垂直延伸沟槽的深度，被设计成提供所需的沟槽侧壁锥角。

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