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21. 发明授权

US06323106B1 Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices 有权
标题翻译：用于半导体器件中氮氧化物形成的双氮注入技术
公开(公告)号：US06323106B1
公开(公告)日：2001-11-27
申请号：US09474666
申请日：1999-12-29
申请人： Shih-Fen Huang , Helmut Puchner
发明人： Shih-Fen Huang , Helmut Puchner
IPC分类号： H01L2176
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/76232 , H01L21/823481
摘要： Provided is a technique for fabrication of a nitrided gate oxide and shallow trench isolation (STI) oxide liner in a semiconductor depletion into STI oxide and the RNCE in CMOS devices by introducing nitrogen to the STI edges of the p-well. This technique improves isolation performance and is also effective to harden the oxide to reduce boron penetration. Nitridization of the STI liner may be conducted on its own or in combination with gate oxide nitridization, both with beneficial effect with regard to the RNCE. The nitridization may also be focussed on the channel region of the gate oxide in particular in order to mitigate RSCE.
摘要翻译：提供了一种在半导体耗尽到STI氧化物中的氮化栅氧化物和浅沟槽隔离（STI）氧化物衬垫的制造技术，以及通过将氮引入到p阱的STI边缘中的CMOS器件中的RNCE。该技术提高了隔离性能，并且还有效地使氧化物硬化以减少硼渗透。 STI衬垫的氮化可以单独进行或与栅氧化物氮化结合进行，对于RNCE都有有益的作用。特别地，氮化也可以集中在栅极氧化物的沟道区上，以减轻RSCE。

22. 发明授权

US6090651A Depletion free polysilicon gate electrodes 有权
标题翻译：无耗多晶硅栅电极
公开(公告)号：US6090651A
公开(公告)日：2000-07-18
申请号：US434340
申请日：1999-11-05
申请人： Helmut Puchner , Sheldon Aronowitz , Gary K. Giust
发明人： Helmut Puchner , Sheldon Aronowitz , Gary K. Giust
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , Y10S438/929
摘要： A method of forming a supersaturated layer on a semiconductor device, where an initial phase layer is deposited on the semiconductor device. The initial phase layer has a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level. A concentration of a dopant is impregnated within the initial phase layers, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level. The initial phase layer is annealed, without appreciably heating the semiconductor device, using an amount of energy that is high enough to liquefy the initial phase layer over a melt duration. This dissolves the dopant in the liquefied initial phase layer. The amount of energy is low enough to not appreciably gasify or ablate the initial phase layer. The liquefied initial phase layer is cooled to freeze the dissolved dopant in a supersaturated, electrically activated concentration, thereby forming the supersaturated layer. An initial phase layer of either polysilicon or amorphous silicon may be deposited over a CMOS device. After laser annealing the initial phase layer with a melt duration of no more than about 100 nanoseconds, it is transformed into a doped polysilicon gate electrode that can be patterned and further processed.
摘要翻译：在半导体器件上形成过饱和层的方法，其中初始相层沉积在半导体器件上。初始相层具有固相掺杂剂饱和水平和液相掺杂剂饱和水平，其中液相掺杂剂饱和水平大于固相掺杂剂饱和水平。掺杂剂的浓度浸渍在初始相层中，其中掺杂剂的浓度大于固相掺杂剂饱和水平并且不大于约液相掺杂剂饱和水平。使用一定量的足够高的能量使熔融持续时间内的初始相层液化的能量，初始相层退火，而不明显地加热半导体器件。这溶解了液化的初始相层中的掺杂剂。能量的量足够低，不能明显地气化或消融初始相层。液化的初始相层被冷却以使过溶化的掺杂剂以过饱和的电活化浓度冷冻，从而形成过饱和层。多晶硅或非晶硅的初始相层可以沉积在CMOS器件上。在熔融持续时间不超过约100纳秒的激光退火初始相层之后，将其转变成可被图案化并进一步处理的掺杂多晶硅栅电极。

23. 发明授权

US08143673B1 Circuit with electrostatic discharge protection 有权
标题翻译：电路具有静电放电保护
公开(公告)号：US08143673B1
公开(公告)日：2012-03-27
申请号：US12435320
申请日：2009-05-04
申请人： Andrew Walker , Helmut Puchner , Kevin Jang
发明人： Andrew Walker , Helmut Puchner , Kevin Jang
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L29/7835
摘要： A circuit with electrostatic discharge protection is described. The circuit includes an output driver transistor with an extended drain contact region. The circuit also includes a distinct device configured to provide electrostatic discharge protection for the output driver transistor. The distinct device includes an electrostatic discharge protection transistor with an extended drain region.
摘要翻译：描述了具有静电放电保护的电路。该电路包括具有扩展的漏极接触区域的输出驱动晶体管。电路还包括被配置为为输出驱动晶体管提供静电放电保护的不同器件。不同的装置包括具有延伸的漏极区域的静电放电保护晶体管。

24. 发明授权

US07936023B1 High voltage diode 有权
标题翻译：高压二极管
公开(公告)号：US07936023B1
公开(公告)日：2011-05-03
申请号：US11861013
申请日：2007-09-25
申请人： Jaejune Jang , Bill Phan , Helmut Puchner
发明人： Jaejune Jang , Bill Phan , Helmut Puchner
IPC分类号： H01L23/62
CPC分类号： H01L29/8611 , H01L29/0634 , H01L29/0653
摘要： A diode, includes a semiconductor substrate, a first region doped with a first dopant type in the substrate, a second region doped with a second dopant type in the substrate, a first well of the first dopant type in the substrate and surrounding the first region and the second region, and a second well of the second dopant type in the substrate connecting the first region and the second region. The first dopant type is opposite the second dopant type.
摘要翻译：二极管包括半导体衬底，在衬底中掺杂有第一掺杂剂类型的第一区域，在衬底中掺杂第二掺杂剂类型的第二区域，衬底中的第一掺杂剂类型的第一阱并围绕第一区域和第二区域，以及在连接第一区域和第二区域的基板中的第二掺杂剂类型的第二阱。第一掺杂剂类型与第二掺杂剂类型相反。

25. 发明申请

US20100041222A1 SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same 有权
标题翻译： SONOS类型堆叠用于非易失性更换存储器件及其形成方法
公开(公告)号：US20100041222A1
公开(公告)日：2010-02-18
申请号：US12413389
申请日：2009-03-27
申请人： Helmut Puchner , Igor Polishchuk , Sagy Levy
发明人： Helmut Puchner , Igor Polishchuk , Sagy Levy
IPC分类号： H01L21/8246
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/792
摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.
摘要翻译：描述了制造非易失性电荷陷阱存储器件的方法。该方法包括在基板的表面上形成第一氧化物层。第一氧化物层暴露于具有第一偏压的第一去耦等离子体氮化工艺。随后，在第一氧化物层上形成电荷俘获层。电荷捕获层暴露于氧化过程，然后暴露于具有第二不同偏压的第二去耦等离子体氮化工艺。

26. 发明授权

US07592661B1 CMOS embedded high voltage transistor 有权
标题翻译： CMOS嵌入式高压晶体管
公开(公告)号：US07592661B1
公开(公告)日：2009-09-22
申请号：US11489047
申请日：2006-07-19
申请人： Sungkwon Lee , Helmut Puchner
发明人： Sungkwon Lee , Helmut Puchner
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/0847 , H01L21/823892 , H01L27/092 , H01L29/1045 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A circuit having a high voltage, drain-extended (DE) metal-oxide-semiconductor (MOS) transistor and method for fabricating the same are provided. Generally, the circuit includes an n-channel (NMOS) transistor having: (i) a source and drain formed in a substrate, the source separated from the drain by a channel; and (ii) a diffused deep n-well (DNW) formed by a long, high temperature drive-in step. The DNW forms a drain-extension region for the NMOS transistor surrounding the drain and extending a predetermined distance into the channel. The drain extension region has a doping concentration lower than the source and drain to deplete during reverse biasing of the transistor, thereby raising a breakdown voltage of the transistor. Preferably, the circuit further includes a DE p-channel MOS (PMOS) transistor in which the DNW forms a well tub for the PMOS transistor, and a p-well in DNW forms a DE region therefore. Other embodiments are also disclosed.
摘要翻译：提供具有高电压，漏极延伸（DE）金属氧化物半导体（MOS）晶体管的电路及其制造方法。通常，电路包括：n沟道（NMOS）晶体管，其具有：（i）在衬底中形成的源极和漏极，源极通过沟道与漏极分离; 和（ii）通过长的高温驱动步骤形成的扩散的深n阱（DNW）。 DNW形成了围绕漏极的NMOS晶体管的漏极扩展区域，并且将预定距离延伸到沟道中。漏极延伸区域具有低于源极和漏极的掺杂浓度以在晶体管的反向偏置期间消耗，从而提高晶体管的击穿电压。优选地，电路还包括DE p沟道MOS（PMOS）晶体管，其中DNW形成用于PMOS晶体管的阱槽，因此在DNW中的p阱形成DE区。还公开了其他实施例。

27. 发明授权

US06727165B1 Fabrication of metal contacts for deep-submicron technologies 有权
标题翻译：用于深亚微米技术的金属触点的制造
公开(公告)号：US06727165B1
公开(公告)日：2004-04-27
申请号：US09967074
申请日：2001-09-28
申请人： Helmut Puchner , Ming-Yi Lee
发明人： Helmut Puchner , Ming-Yi Lee
IPC分类号： H01L2144
CPC分类号： H01L21/2855 , H01L21/28518
摘要： Provided is a process for forming a semiconductor device having salicided contacts. A concentration of metal is formed at the substrate surface by exposing the substrate to a metal plasma. The concentration of metal is then annealed to produce a salicided contact. In a separate embodiment, the metallization plasma and salicide anneal occur in-situ in one process step.
摘要翻译：提供了一种用于形成具有水银触点的半导体器件的工艺。通过将衬底暴露于金属等离子体，在衬底表面上形成金属的浓度。然后将金属的浓度退火以产生水银触点。在单独的实施例中，金属化等离子体和自对准硅化物退火在一个工艺步骤中原位发生。

28. 发明授权

US06544854B1 Silicon germanium CMOS channel 有权
公开(公告)号：US06544854B1
公开(公告)日：2003-04-08
申请号：US09724444
申请日：2000-11-28
申请人： Helmut Puchner , Gary K. Giust
发明人： Helmut Puchner , Gary K. Giust
IPC分类号： H01L21336
CPC分类号： H01L29/66651 , H01L29/1054 , H01L29/165 , H01L29/7833 , Y10S438/933
摘要： A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source-drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal. Thus, standard materials for the spacer, such as silicon oxide or silicon nitride are not preferred for this application, because they tend to be transparent to the laser beam emissions.

29. 发明授权

US06504219B1 Indium field implant for punchthrough protection in semiconductor devices 有权
标题翻译：用于半导体器件穿透保护的铟场植入物
公开(公告)号：US06504219B1
公开(公告)日：2003-01-07
申请号：US09960765
申请日：2001-09-21
申请人： Helmut Puchner , Shih-Fen Huang
发明人： Helmut Puchner , Shih-Fen Huang
IPC分类号： H01L27095
CPC分类号： H01L21/8238 , H01L21/76237
摘要： Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.
摘要翻译：提供了一种用于在STI沟槽底部形成铟场注入的技术，以加强场氧化物下的p阱，但不会削弱场氧化物下的n阱。铟的扩散系数比硼的扩散系数小一个数量级，铟的激活电位足够高以使阱掺杂。因此，即使在硼耗尽的情况下，注入的铟能够在场隔离下保持p-n阱结的p型掺杂浓度，并且氧化物/硅界面也能保持高浓度，从而避免穿透。

30. 发明授权

US06486064B1 Shallow junction formation 有权
公开(公告)号：US06486064B1
公开(公告)日：2002-11-26
申请号：US09670448
申请日：2000-09-26
申请人： Helmut Puchner
发明人： Helmut Puchner
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L21/3144 , H01L21/31662 , H01L21/3211 , Y10S438/914 , Y10S438/957
摘要： A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer. The impregnation is accomplished using a process that does not impregnate a significant amount of the first species in the exposed vertical faces of the gate electrode. The impregnated sacrificial layer, the exposed vertical faces of the gate electrode, and the impregnated exposed portions of the gate dielectric layer are exposed to an oxidizing environment, causing oxide growth on at least the exposed vertical faces of the gate electrode, and thereby covering the vertical faces of the gate electrode with oxide sidewalls. However, the oxidizing environment does not cause significant oxide growth under the impregnated sacrificial layer and the impregnated exposed portions of the gate dielectric layer. A second species is impregnated through the impregnated exposed portions of the gate dielectric layer into portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer. The impregnated second species forms junctions in the portions of the semiconductor substrate that underlie the impregnated exposed portions of the gate dielectric layer.

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